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Description
  • Článek popisuje kompletní obvodovou realizaci vyvíjející se kombinační jednotky pro FPGA. Navržená jednotka sestávající z virtuálního rekonfigurovatelného obvodu a evolučního algoritmu byla popsána ve VHDL nezávisle na cílové platformě, tj. jako soft IPcore, a implementována na kartě Combo6. Jednotka je schopna automaticky vyevolvovat realizaci požadované kombinační funkce pouze na základě interakce s prostředím. (cs)
  • A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A numberr of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specifiedby randomly generated truth tables. <br>
  • A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A numberr of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specifiedby randomly generated truth tables. <br> (en)
Title
  • An Evolvable Combinational Unit for FPGAs
  • An Evolvable Combinational Unit for FPGAs (en)
  • Vyvíjející se kombinační jednotka pro FPGA (cs)
skos:prefLabel
  • An Evolvable Combinational Unit for FPGAs
  • An Evolvable Combinational Unit for FPGAs (en)
  • Vyvíjející se kombinační jednotka pro FPGA (cs)
skos:notation
  • RIV/00216305:26230/04:PU50053!RIV/2005/GA0/262305/N
http://linked.open.../vavai/riv/strany
  • 461-486
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/04/0737), P(GP102/03/P004)
http://linked.open...iv/cisloPeriodika
  • 5
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 554098
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/04:PU50053
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • combinational circuit, evolutionary design, evolvable hardware, field programmable gate array<br> (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...odStatuVydavatele
  • SK - Slovenská republika
http://linked.open...ontrolniKodProRIV
  • [919AFC273FBA]
http://linked.open...i/riv/nazevZdroje
  • Computing and Informatics
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...v/svazekPeriodika
  • 23
http://linked.open...iv/tvurceVysledku
  • Sekanina, Lukáš
  • Friedl, Štěpán
issn
  • 1335-9150
number of pages
http://localhost/t...ganizacniJednotka
  • 26230
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