| Attributes | Values |
|---|
| rdf:type
| |
| Description
| - A highly efficient test schedule can be created for a given digital circuit if a proper test-scheduling algorithm is selected and if the circuit fulfils several criteria that affect the quality of a resulting test schedule significantly and independently on any scheduling algorithm. If a design for testability techniques are applied to the circuit structure, the way in which they are applied have a big impact on those circuit properties. Thus, it is feasible to deal with the relation between applicationn of selected design for testability techniques and the quality of a resulting test schedule in detail. This is a wide research area. Our paper deals with the register selection technique through which a test will be applied. The paper presents a methodology for selecting registers for the test application in such a way that the cardinality of a set of selected registers is minimized and test resources allocated to functional units are shared in a maximum way. Proposed methodology is mathematically desc
- A highly efficient test schedule can be created for a given digital circuit if a proper test-scheduling algorithm is selected and if the circuit fulfils several criteria that affect the quality of a resulting test schedule significantly and independently on any scheduling algorithm. If a design for testability techniques are applied to the circuit structure, the way in which they are applied have a big impact on those circuit properties. Thus, it is feasible to deal with the relation between applicationn of selected design for testability techniques and the quality of a resulting test schedule in detail. This is a wide research area. Our paper deals with the register selection technique through which a test will be applied. The paper presents a methodology for selecting registers for the test application in such a way that the cardinality of a set of selected registers is minimized and test resources allocated to functional units are shared in a maximum way. Proposed methodology is mathematically desc (en)
- Pokud je zvolen vhodný plánovací algoritmus a daný obvod splňuje jistá kritéria, je možné pro daný číslicový obvod vytvořit vysoce efektivní plán testu. Byl-li daný obvod modifikován pomocí technik návrhu pro snadnou testovatelnost, pak způsob aplikace těchto technik má podstatný vliv na parametry obvodu. Tedy je výhodné podrobněji se zabývat vlivem způsobu aplikace technik pro snadnou testovatelnost na výsledný plán testu. Tento článek se zabývá otázkou vlivu techniky výběru registrů do scan řetězzů na plán testu. Ve článku je představen postup výběru registrů do scan řetězů takovým způsobem, aby výsledná množina scan registrů byla minimální a aby vybrané registry, tj. prostředky pro testování komponent obvodu, byly maximálně sdíleny obvodovými komponentami. Metoda je popsána pomocí prostředků matematického modelu, definice jsou ilustrovány na vhodných příkladech a experimentální výsledky jsou shrnuty spolu s výhledem další výzkumné činnosti v této oblasti. (cs)
|
| Title
| - Identifikace registrů v RTL obvodech (cs)
- The Identification of Registers in RTL Structures
- The Identification of Registers in RTL Structures (en)
|
| skos:prefLabel
| - Identifikace registrů v RTL obvodech (cs)
- The Identification of Registers in RTL Structures
- The Identification of Registers in RTL Structures (en)
|
| skos:notation
| - RIV/00216305:26230/04:PU49270!RIV/2005/GA0/262305/N
|
| http://linked.open.../vavai/riv/strany
| |
| http://linked.open...avai/riv/aktivita
| |
| http://linked.open...avai/riv/aktivity
| |
| http://linked.open...vai/riv/dodaniDat
| |
| http://linked.open...aciTvurceVysledku
| |
| http://linked.open.../riv/druhVysledku
| |
| http://linked.open...iv/duvernostUdaju
| |
| http://linked.open...titaPredkladatele
| |
| http://linked.open...dnocenehoVysledku
| |
| http://linked.open...ai/riv/idVysledku
| - RIV/00216305:26230/04:PU49270
|
| http://linked.open...riv/jazykVysledku
| |
| http://linked.open.../riv/klicovaSlova
| - digital circuit diagnosis, test scheduling, resource selection, register resources, discrete mathematics, graph, relation, Hasse diagram, coverage problem, set minimization, register-transfer level (en)
|
| http://linked.open.../riv/klicoveSlovo
| |
| http://linked.open...ontrolniKodProRIV
| |
| http://linked.open...v/mistoKonaniAkce
| - Amathus hotel, Poseidon avenue, 8098 Paphos
|
| http://linked.open...i/riv/mistoVydani
| |
| http://linked.open...i/riv/nazevZdroje
| - Preliminary Proceedings of 1st International Symposium on Leveraging Applications of Formal Methods ISOLA 2004
|
| http://linked.open...in/vavai/riv/obor
| |
| http://linked.open...ichTvurcuVysledku
| |
| http://linked.open...cetTvurcuVysledku
| |
| http://linked.open...vavai/riv/projekt
| |
| http://linked.open...UplatneniVysledku
| |
| http://linked.open...iv/tvurceVysledku
| - Kotásek, Zdeněk
- Strnadel, Josef
- Mika, Daniel
|
| http://linked.open...vavai/riv/typAkce
| |
| http://linked.open.../riv/zahajeniAkce
| |
| number of pages
| |
| http://purl.org/ne...btex#hasPublisher
| - Department of Computer Science of University of Cyprus
|
| https://schema.org/isbn
| |
| http://localhost/t...ganizacniJednotka
| |
![[RDF Data]](/fct/images/sw-rdf-blue.png)
![[cxml]](/fct/images/cxml_doc.png)
![[csv]](/fct/images/csv_doc.png)
![[text]](/fct/images/ntriples_doc.png)
![[turtle]](/fct/images/n3turtle_doc.png)
![[ld+json]](/fct/images/jsonld_doc.png)
![[rdf+json]](/fct/images/json_doc.png)
![[rdf+xml]](/fct/images/xml_doc.png)
![[atom+xml]](/fct/images/atom_doc.png)
![[html]](/fct/images/html_doc.png)