About: RTL Testability Verification System

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Description	This paper discusses register transfer level (RTL) digital circuit design testability verification. Digital circuit design testability verification is used to judge if the digital circuit design, analyzed and eventually modified by method leading to partial scan, is really testable. This is because the method utilizes I-paths, but doesn't take into account dependencies of these I-paths. So there conflicts and deadlocks may appear when these I-paths in the circuit are set up. The RTL digital circuit design testability verification detects this problem. The main goal of this work is to develop and implement software system for automatic testability verification of register transfer level digital circuit design. In the implementation of the system, a C/E Petri Nets approach is used. The input to the system is formal specification of digital circuit design and list of digital circuit design modifications (scan chain), the output from the system is the decision if the circuit is testable or not. If the sys This paper discusses register transfer level (RTL) digital circuit design testability verification. Digital circuit design testability verification is used to judge if the digital circuit design, analyzed and eventually modified by method leading to partial scan, is really testable. This is because the method utilizes I-paths, but doesn't take into account dependencies of these I-paths. So there conflicts and deadlocks may appear when these I-paths in the circuit are set up. The RTL digital circuit design testability verification detects this problem. The main goal of this work is to develop and implement software system for automatic testability verification of register transfer level digital circuit design. In the implementation of the system, a C/E Petri Nets approach is used. The input to the system is formal specification of digital circuit design and list of digital circuit design modifications (scan chain), the output from the system is the decision if the circuit is testable or not. If the sys (en)
Title	RTL Testability Verification System RTL Testability Verification System (en)
skos:prefLabel	RTL Testability Verification System RTL Testability Verification System (en)
skos:notation	RIV/00216305:26230/04:PU49213!RIV11-MSM-26230___
http://linked.open...avai/riv/aktivita	N P V Z
http://linked.open...avai/riv/aktivity	N, P(GA102/04/0737), P(GP102/03/P176), V, Z(MSM 262200012)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Růžička, Richard Škarvada, Jaroslav
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	585272
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/04:PU49213
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Testability, Verification, RTL Design, I Path, Diagnostics (en)
http://linked.open.../riv/klicoveSlovo	Verification Diagnostics Testability I Path RTL Design
http://linked.open...ontrolniKodProRIV	[547BE787887D]
http://linked.open...v/mistoKonaniAkce	Rennes
http://linked.open...i/riv/mistoVydani	Linz
http://linked.open...i/riv/nazevZdroje	Proceedings of the Work In Progress Session of 30th Euromicro Conference
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Modern methods of digital system synthesis Formal approach to digital circuits test scheduling
http://linked.open...UplatneniVysledku	2004
http://linked.open...iv/tvurceVysledku	Růžička, Richard Škarvada, Jaroslav
http://linked.open...vavai/riv/typAkce	EUR - Evropská
http://linked.open.../riv/zahajeniAkce	2004-08-31 (xsd:date)
http://linked.open...n/vavai/riv/zamer	http://linked.opendata.cz/resource/domain/vavai/zamer/MSM%20262200012
number of pages	2 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Johannes Kepler University Linz
https://schema.org/isbn	3-902457-05-8
http://localhost/t...ganizacniJednotka	26230

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