About: Formal Approach to Synthesis of a Test Controller

Facets (new session)
Description
Metadata
Settings
- owl:sameAs
- Inference Rule:

About: Formal Approach to Synthesis of a Test Controller Goto Sponge NotDistinct Permalink

An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In the paper, a method for formal construction of a test controller of the RT level digital circuit is presented. As input, a digital circuit structure at RT level designed using any DfT technique is assumed. The proposed method enables to create a Finite State Machine with output, which can control all enable, address and clock inputs of circuit elements during the test application process. It is assumed that test patterns are inserted to circuit primary input ports and transferred through the circuit structure to selected points inside the circuit, to which they must be applied. Responses to these test patterns must then be transferred outside of the circuit and analyzed. Transfers of such diagnostic data are controlled by the test controller. Formal tools and approaches are used. The main advantage of formally described methods is that all processes are easily provable and no large evaluation of proposed methods on benchmark circuits is necessary. In the paper, a method for formal construction of a test controller of the RT level digital circuit is presented. As input, a digital circuit structure at RT level designed using any DfT technique is assumed. The proposed method enables to create a Finite State Machine with output, which can control all enable, address and clock inputs of circuit elements during the test application process. It is assumed that test patterns are inserted to circuit primary input ports and transferred through the circuit structure to selected points inside the circuit, to which they must be applied. Responses to these test patterns must then be transferred outside of the circuit and analyzed. Transfers of such diagnostic data are controlled by the test controller. Formal tools and approaches are used. The main advantage of formally described methods is that all processes are easily provable and no large evaluation of proposed methods on benchmark circuits is necessary. (en)
Title	Formal Approach to Synthesis of a Test Controller Formal Approach to Synthesis of a Test Controller (en)
skos:prefLabel	Formal Approach to Synthesis of a Test Controller Formal Approach to Synthesis of a Test Controller (en)
skos:notation	RIV/00216305:26230/04:PU49146!RIV11-MSM-26230___
http://linked.open...avai/riv/aktivita	N P V Z
http://linked.open...avai/riv/aktivity	N, P(GA102/04/0737), P(GP102/03/P176), V, Z(MSM 262200012)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Růžička, Richard Tupec, Pavel
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	564687
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/04:PU49146
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Testability, Test Controller, Automata, I path (en)
http://linked.open.../riv/klicoveSlovo	Testability Test Controller Automata I path
http://linked.open...ontrolniKodProRIV	[BF0976FBFCA8]
http://linked.open...v/mistoKonaniAkce	Brno
http://linked.open...i/riv/mistoVydani	Los Alamitos, California
http://linked.open...i/riv/nazevZdroje	Proceedings of Eleventh International Conference and Workshop on the Engineering of Computer-Based Systems
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Modern methods of digital system synthesis Formal approach to digital circuits test scheduling
http://linked.open...UplatneniVysledku	2004
http://linked.open...iv/tvurceVysledku	Růžička, Richard Tupec, Pavel
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2004-05-23 (xsd:date)
http://linked.open...n/vavai/riv/zamer	http://linked.opendata.cz/resource/domain/vavai/zamer/MSM%20262200012
number of pages	8 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	0-7695-2125-8
http://localhost/t...ganizacniJednotka	26230

Faceted Search & Find service v1.16.118 as of Jun 21 2024

Alternative Linked Data Documents: ODE Content Formats:

RDF

ODATA

Microdata

About

OpenLink Virtuoso version 07.20.3240 as of Jun 21 2024, on Linux (x86_64-pc-linux-gnu), Single-Server Edition (126 GB total memory, 58 GB memory in use)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2024 OpenLink Software