About: Test scheduling for embedded systems

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The paper proposes two approaches to test scheduling. The first one utilizes the concept of TACG (Test Application Conflict Graph). For the testing process the resource utilization model is defined and used for the TACG construction. Different conflicts that must be taken into account during test scheduling are presented. The paper offers a methodology that can be utilized during embedded test design process, the final goal of which is to reduce the overall test application time and power consumption during the test application. The second methodology is based on optimising the test schedule - the test application time, TAM width and power consumption are taken into account during the process. The goal of the methodology is a reasonable trade-off between these parameters. The paper proposes two approaches to test scheduling. The first one utilizes the concept of TACG (Test Application Conflict Graph). For the testing process the resource utilization model is defined and used for the TACG construction. Different conflicts that must be taken into account during test scheduling are presented. The paper offers a methodology that can be utilized during embedded test design process, the final goal of which is to reduce the overall test application time and power consumption during the test application. The second methodology is based on optimising the test schedule - the test application time, TAM width and power consumption are taken into account during the process. The goal of the methodology is a reasonable trade-off between these parameters. (en)
Title	Test scheduling for embedded systems Test scheduling for embedded systems (en)
skos:prefLabel	Test scheduling for embedded systems Test scheduling for embedded systems (en)
skos:notation	RIV/00216305:26230/03:PU42590!RIV11-MSM-26230___
http://linked.open...avai/riv/aktivita	N P V Z
http://linked.open...avai/riv/aktivity	N, P(GA102/01/1531), V, Z(MSM 262200012)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Mika, Daniel Kotásek, Zdeněk Strnadel, Josef
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	630703
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/03:PU42590
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	TACG, genetic algorithm, embedded systems (en)
http://linked.open.../riv/klicoveSlovo	genetic algorithm embedded systems TACG
http://linked.open...ontrolniKodProRIV	[210286C1BF53]
http://linked.open...v/mistoKonaniAkce	Belek
http://linked.open...i/riv/mistoVydani	Belek
http://linked.open...i/riv/nazevZdroje	Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Formal approaches in digital circuit diagnostics - testable design verification
http://linked.open...UplatneniVysledku	2003
http://linked.open...iv/tvurceVysledku	Kotásek, Zdeněk Strnadel, Josef Mika, Daniel
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2003-09-02 (xsd:date)
http://linked.open...n/vavai/riv/zamer	http://linked.opendata.cz/resource/domain/vavai/zamer/MSM%20262200012
number of pages	5 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society Press
https://schema.org/isbn	0-7695-2003-0
http://localhost/t...ganizacniJednotka	26230

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