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  • The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectual Property) cores. The cores should be reused in the same way as ordinary IP cores are reused. In contrast to the conventional cores, the evolvable cores are able to perform autonomous evolution of their internal circuits. The cores should be available in the form of HDL source code, i.e. they should be synthesizable into any reconfigurable device of a sufficient capacity. The approach is based on implementation of a virtual reconfigurable circuit and a genetic unit in an ordinary FPGA. In the presented case study an adaptive image filter is designed, implemented and synthesized. The proposed idea of evolvable IP core could open the way towards defining a business model for evolvable hardware.
  • The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectual Property) cores. The cores should be reused in the same way as ordinary IP cores are reused. In contrast to the conventional cores, the evolvable cores are able to perform autonomous evolution of their internal circuits. The cores should be available in the form of HDL source code, i.e. they should be synthesizable into any reconfigurable device of a sufficient capacity. The approach is based on implementation of a virtual reconfigurable circuit and a genetic unit in an ordinary FPGA. In the presented case study an adaptive image filter is designed, implemented and synthesized. The proposed idea of evolvable IP core could open the way towards defining a business model for evolvable hardware. (en)
Title
  • Towards Evolvable IP Cores for FPGAs
  • Towards Evolvable IP Cores for FPGAs (en)
skos:prefLabel
  • Towards Evolvable IP Cores for FPGAs
  • Towards Evolvable IP Cores for FPGAs (en)
skos:notation
  • RIV/00216305:26230/03:PU42538!RIV11-MSM-26230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • N, P(GP102/03/P004), V, Z(MSM 262200012)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 631198
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/03:PU42538
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • evolvable hardware, IP core, digital circuit (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [1B3225CEF7B5]
http://linked.open...v/mistoKonaniAkce
  • Chicago
http://linked.open...i/riv/mistoVydani
  • Los Alamitos
http://linked.open...i/riv/nazevZdroje
  • Proc. of The 2003 NASA/DoD Conference on Evolvable Hardware
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Sekanina, Lukáš
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE Computer Society Press
https://schema.org/isbn
  • 0-7695-1977-6
http://localhost/t...ganizacniJednotka
  • 26230
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