About: The Test Controller Model Based on The Timed Automaton

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In the paper the process of the test controller model design and synthesis on Register Transfer Level (RTL) is described. The principles of test application to circuit element by the test controller model is discussed. The problem of I-path is explained. The formal tool - the timed automaton - is used as a suitable tool for test controller model. In the end of paper there is a simple example of timed automaton, which represents a model of particular behavior of the test controller. In the paper the process of the test controller model design and synthesis on Register Transfer Level (RTL) is described. The principles of test application to circuit element by the test controller model is discussed. The problem of I-path is explained. The formal tool - the timed automaton - is used as a suitable tool for test controller model. In the end of paper there is a simple example of timed automaton, which represents a model of particular behavior of the test controller. (en)
Title	The Test Controller Model Based on The Timed Automaton The Test Controller Model Based on The Timed Automaton (en)
skos:prefLabel	The Test Controller Model Based on The Timed Automaton The Test Controller Model Based on The Timed Automaton (en)
skos:notation	RIV/00216305:26230/03:PU42526!RIV11-MSM-26230___
http://linked.open...avai/riv/aktivita	N V Z
http://linked.open...avai/riv/aktivity	N, V, Z(MSM 262200012)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Mika, Daniel Kotásek, Zdeněk
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	630695
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/03:PU42526
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Register Transfer Level (RTL), Circuit Under Test (CUT), Test Controller Model (en)
http://linked.open.../riv/klicoveSlovo	Circuit Under Test (CUT) Register Transfer Level (RTL) Test Controller Model
http://linked.open...ontrolniKodProRIV	[744B7D76CC63]
http://linked.open...v/mistoKonaniAkce	Brno
http://linked.open...i/riv/mistoVydani	Ostrava
http://linked.open...i/riv/nazevZdroje	Proceedings of 37th International Conference MOSIS´03 Modelling and Simulation of Systems
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...UplatneniVysledku	2003
http://linked.open...iv/tvurceVysledku	Kotásek, Zdeněk Mika, Daniel
http://linked.open...vavai/riv/typAkce	EUR - Evropská
http://linked.open.../riv/zahajeniAkce	2003-04-28 (xsd:date)
http://linked.open...n/vavai/riv/zamer	http://linked.opendata.cz/resource/domain/vavai/zamer/MSM%20262200012
number of pages	8 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Neuveden
https://schema.org/isbn	80-85988-86-0
http://localhost/t...ganizacniJednotka	26230

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