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  • In the paper the process of the test controller design and synthesis on register transfer level is described. The principle of circuit element access is discussed during the test plan scheduling. The formal tool - a mathematical logic and a set theory - is used as suitable tool for test controller design process. The problem of I-path is explained and a simple example of I-path is also demonstrated.
  • In the paper the process of the test controller design and synthesis on register transfer level is described. The principle of circuit element access is discussed during the test plan scheduling. The formal tool - a mathematical logic and a set theory - is used as suitable tool for test controller design process. The problem of I-path is explained and a simple example of I-path is also demonstrated. (en)
Title
  • The Test Controller Design Based on I-Path Concept
  • The Test Controller Design Based on I-Path Concept (en)
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  • The Test Controller Design Based on I-Path Concept
  • The Test Controller Design Based on I-Path Concept (en)
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  • RIV/00216305:26230/03:PU42522!RIV11-MSM-26230___
http://linked.open...avai/riv/aktivita
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  • N, V, Z(MSM 262200012)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
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  • 630694
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  • RIV/00216305:26230/03:PU42522
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  • Register Transfer Level, I-path, I-mode, Circuit Under Test (en)
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  • [5A8F3D0C7CF1]
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  • Brno
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  • Brno
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  • Proceedings of 9th Conference and Competition STUDENT EEICT 2003 Volume 3
http://linked.open...in/vavai/riv/obor
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  • Mika, Daniel
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http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
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  • Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
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  • 80-214-2379-X
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  • 26230
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