About: Nested Loops Degree Impact on RTL Digital Circuit Testability

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The existence of loops in a circuit structure causes problems in both test generation and application. Thus, the problem of identifying loops becomes an important task during testability analysis or, later, e.g., during allocation-for testability process. When nested loops occur in the circuit, it is necessary to accurately determine the most nested one to improve circuit testability significantly, with minimal design cost. This paper deals with the problem of identifying nested loops including their neesting degree in the register-transfer level (RTL) digital circuit structure as well as with the impact of such loops on the circuit testability. The existence of loops in a circuit structure causes problems in both test generation and application. Thus, the problem of identifying loops becomes an important task during testability analysis or, later, e.g., during allocation-for testability process. When nested loops occur in the circuit, it is necessary to accurately determine the most nested one to improve circuit testability significantly, with minimal design cost. This paper deals with the problem of identifying nested loops including their neesting degree in the register-transfer level (RTL) digital circuit structure as well as with the impact of such loops on the circuit testability. (en)
Title	Nested Loops Degree Impact on RTL Digital Circuit Testability Nested Loops Degree Impact on RTL Digital Circuit Testability (en)
skos:prefLabel	Nested Loops Degree Impact on RTL Digital Circuit Testability Nested Loops Degree Impact on RTL Digital Circuit Testability (en)
skos:notation	RIV/00216305:26230/03:PU42507!RIV/2004/GA0/262304/N
http://linked.open.../vavai/riv/strany	202-207
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(GA102/01/1531)
http://linked.open...vai/riv/dodaniDat	2004
http://linked.open...aciTvurceVysledku	Strnadel, Josef
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	617686
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/03:PU42507
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Testability, feedback loop, directed graph, ordered set, graph algorithm (en)
http://linked.open.../riv/klicoveSlovo	directed graph ordered set Testability feedback loop graph algorithm
http://linked.open...ontrolniKodProRIV	[2505000ED7B4]
http://linked.open...v/mistoKonaniAkce	Ostrava
http://linked.open...i/riv/mistoVydani	Oxford
http://linked.open...i/riv/nazevZdroje	Programmable Devices and Systems
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	1 (xsd:int)
http://linked.open...ocetUcastnikuAkce	0 (xsd:int)
http://linked.open...nichUcastnikuAkce	0 (xsd:int)
http://linked.open...vavai/riv/projekt	Formal approaches in digital circuit diagnostics - testable design verification
http://linked.open...UplatneniVysledku	2003
http://linked.open...iv/tvurceVysledku	Strnadel, Josef
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2003-02-11 (xsd:date)
number of pages	6 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Elsevier Science
https://schema.org/isbn	0-08-044130-0
http://localhost/t...ganizacniJednotka	26230

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