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Description
  • Scheduling is the most important task in high-level synthesis process, while pipelining is highly important for realising high-performance digital components. This paper presents a pipeline list-based scheduling algorithm, which performs forward and backward pipelining. The forward priority function is based on incorporating some information extracted from data flow graph (DFG) structure to guide the scheduler to find near-optimal/optimal schedules quickly. The algorithm has a flexible procedure cycle, which allows designers to make efficient area-performance trade-offs by using different strategies employed. Designers can choose between doing forward / backward pipelining with or without resource sharing combined with clock cycle selection, pipe stage delay determination. Experimental results with standard benchmarks show the effectiveness of the proposed algorithm.
  • Scheduling is the most important task in high-level synthesis process, while pipelining is highly important for realising high-performance digital components. This paper presents a pipeline list-based scheduling algorithm, which performs forward and backward pipelining. The forward priority function is based on incorporating some information extracted from data flow graph (DFG) structure to guide the scheduler to find near-optimal/optimal schedules quickly. The algorithm has a flexible procedure cycle, which allows designers to make efficient area-performance trade-offs by using different strategies employed. Designers can choose between doing forward / backward pipelining with or without resource sharing combined with clock cycle selection, pipe stage delay determination. Experimental results with standard benchmarks show the effectiveness of the proposed algorithm. (en)
Title
  • A Pipeline Scheduling Algorithm for High-Level Synthesis
  • A Pipeline Scheduling Algorithm for High-Level Synthesis (en)
skos:prefLabel
  • A Pipeline Scheduling Algorithm for High-Level Synthesis
  • A Pipeline Scheduling Algorithm for High-Level Synthesis (en)
skos:notation
  • RIV/00216305:26230/03:PU42504!RIV/2004/GA0/262304/N
http://linked.open.../vavai/riv/strany
  • 178-183
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/01/1531)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
  • Sllame M., Azeddien
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 597056
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/03:PU42504
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • pipelines, algorithms, synthesis, architecture, computer-aided design. (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [0A413E3EB740]
http://linked.open...v/mistoKonaniAkce
  • Ostrava
http://linked.open...i/riv/mistoVydani
  • Ostrava
http://linked.open...i/riv/nazevZdroje
  • Proc. of IFAC Workshop on Programmable Devices and Systems Conference
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...ocetUcastnikuAkce
http://linked.open...nichUcastnikuAkce
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Sllame M., Azeddien
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
number of pages
http://purl.org/ne...btex#hasPublisher
  • Neuveden
http://localhost/t...ganizacniJednotka
  • 26230
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