About: Generating PWM Signals With Variable Duty From 0% to 100% Based FPGA SPARTAN3AN

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This article deals with the generation PWM signals with variable duty from 0% to 100% using VHDL and its application in field programmable gate arrays. The article also discusses the usage DCM for decrease the clock frequency. DCM is a digital clock manager that is useful to decrease the skew of clk signal when we want to divide the clk frequency. We used a fixed frequency to produce the input data that generate the PWM signals using one comparator. The comparator compares between two input data. First data is generated using PWM counter and second data is generated by up-down counter using two push buttons. PWM has a fixed frequency and a variable voltage. This voltage value changes for 0V to 2.5 V. Inside signals are monitored on the computer by platform cable usbII and ChipScope program. We need a board fpga and ISE package version14.4. This article deals with the generation PWM signals with variable duty from 0% to 100% using VHDL and its application in field programmable gate arrays. The article also discusses the usage DCM for decrease the clock frequency. DCM is a digital clock manager that is useful to decrease the skew of clk signal when we want to divide the clk frequency. We used a fixed frequency to produce the input data that generate the PWM signals using one comparator. The comparator compares between two input data. First data is generated using PWM counter and second data is generated by up-down counter using two push buttons. PWM has a fixed frequency and a variable voltage. This voltage value changes for 0V to 2.5 V. Inside signals are monitored on the computer by platform cable usbII and ChipScope program. We need a board fpga and ISE package version14.4. (en)
Title	Generating PWM Signals With Variable Duty From 0% to 100% Based FPGA SPARTAN3AN Generating PWM Signals With Variable Duty From 0% to 100% Based FPGA SPARTAN3AN (en)
skos:prefLabel	Generating PWM Signals With Variable Duty From 0% to 100% Based FPGA SPARTAN3AN Generating PWM Signals With Variable Duty From 0% to 100% Based FPGA SPARTAN3AN (en)
skos:notation	RIV/00216305:26220/13:PU106855!RIV15-MSM-26220___
http://linked.open...avai/riv/aktivita	P S
http://linked.open...avai/riv/aktivity	P(ED0014/01/01), S
http://linked.open...iv/cisloPeriodika	4
http://linked.open...vai/riv/dodaniDat	2015
http://linked.open...aciTvurceVysledku	Klíma, Bohumil Knobloch, Jan Nouman, Ziad
http://linked.open.../riv/druhVysledku	J - Článek v odborném periodiku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	76331
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/13:PU106855
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	PWM modulator, FPGA (en)
http://linked.open.../riv/klicoveSlovo	PWM modulator FPGA
http://linked.open...odStatuVydavatele	CZ - Česká republika
http://linked.open...ontrolniKodProRIV	[B626775B641A]
http://linked.open...i/riv/nazevZdroje	Elektrorevue - Internetový časopis (http://www.elektrorevue.cz)
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Research and Technology Centre of Renewable Energy Sources
http://linked.open...UplatneniVysledku	2013
http://linked.open...v/svazekPeriodika	4
http://linked.open...iv/tvurceVysledku	Klíma, Bohumil Knobloch, Jan Nouman, Ziad
issn	1213-1539
number of pages	5 (xsd:int)
http://localhost/t...ganizacniJednotka	26220

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