About: Design and Implementation A Digital Sine-Cosine Generator Based FPGA

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This article proposes a new way to generate a sine and cosine waves based FPGA. These signals can be used to generate a PWM signals that can be used in SDR and DSP. It can be used in control system like control DC and AC motors. The problem is how can generate a sine and cosine waves that are composed of the positive and negative part. Any hardware accepts the values 0, 1 and can't accept the negative values, we used the mode two's components of numbers to represent the positive and negative samples and converted these results to decimal numbers, and we shifted a one half wave 8 bit to obtain the wave without distortion. We used MATLAB to generate the data of sine and cosine wave. We saved the data in ROM memory using VHDL language and we applied the results onto board spartan-3A FPGA. This article proposes a new way to generate a sine and cosine waves based FPGA. These signals can be used to generate a PWM signals that can be used in SDR and DSP. It can be used in control system like control DC and AC motors. The problem is how can generate a sine and cosine waves that are composed of the positive and negative part. Any hardware accepts the values 0, 1 and can't accept the negative values, we used the mode two's components of numbers to represent the positive and negative samples and converted these results to decimal numbers, and we shifted a one half wave 8 bit to obtain the wave without distortion. We used MATLAB to generate the data of sine and cosine wave. We saved the data in ROM memory using VHDL language and we applied the results onto board spartan-3A FPGA. (en)
Title	Design and Implementation A Digital Sine-Cosine Generator Based FPGA Design and Implementation A Digital Sine-Cosine Generator Based FPGA (en)
skos:prefLabel	Design and Implementation A Digital Sine-Cosine Generator Based FPGA Design and Implementation A Digital Sine-Cosine Generator Based FPGA (en)
skos:notation	RIV/00216305:26220/13:PU104158!RIV14-MSM-26220___
http://linked.open...avai/predkladatel	Fakulta elektrotechniky a komunikačních technologií
http://linked.open...avai/riv/aktivita	S
http://linked.open...avai/riv/aktivity	S
http://linked.open...iv/cisloPeriodika	5
http://linked.open...vai/riv/dodaniDat	2014
http://linked.open...aciTvurceVysledku	Klíma, Bohumil Knobloch, Jan Nouman, Ziad
http://linked.open.../riv/druhVysledku	J - Článek v odborném periodiku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	68543
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/13:PU104158
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	comparator, counter, sine and cosine generator, lookup table, PWM, rom memory, VHDL (en)
http://linked.open.../riv/klicoveSlovo	rom memory sine and cosine generator VHDL lookup table PWM counter comparator
http://linked.open...odStatuVydavatele	IN - Indická republika
http://linked.open...ontrolniKodProRIV	[1A113CCCCA81]
http://linked.open...i/riv/nazevZdroje	International Journal of Engineering and Advanced Technology (IJEAT)
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...UplatneniVysledku	2013
http://linked.open...v/svazekPeriodika	2
http://linked.open...iv/tvurceVysledku	Klíma, Bohumil Knobloch, Jan Nouman, Ziad
issn	2249-8958
number of pages	4 (xsd:int)
http://localhost/t...ganizacniJednotka	26220

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