About: FPGA Based 1 Gbps Ethernet Header Detector

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This paper presents a study about a hardware implementation of the Ethernet header detector implemented in FPGA circuits. The header detector is able to detect the TCP/IP and UDP/IP header contents for both the IPv4 and the IPv6 protocols. This hardware implementation allows access to the headers content faster than the software implementation. Therefore, it is suitable for many different high-speed Ethernet devices. This paper presents a study about a hardware implementation of the Ethernet header detector implemented in FPGA circuits. The header detector is able to detect the TCP/IP and UDP/IP header contents for both the IPv4 and the IPv6 protocols. This hardware implementation allows access to the headers content faster than the software implementation. Therefore, it is suitable for many different high-speed Ethernet devices. (en)
Title	FPGA Based 1 Gbps Ethernet Header Detector FPGA Based 1 Gbps Ethernet Header Detector (en)
skos:prefLabel	FPGA Based 1 Gbps Ethernet Header Detector FPGA Based 1 Gbps Ethernet Header Detector (en)
skos:notation	RIV/00216305:26220/12:PU99568!RIV13-MSM-26220___
http://linked.open...avai/predkladatel	Fakulta elektrotechniky a komunikačních technologií
http://linked.open...avai/riv/aktivita	S
http://linked.open...avai/riv/aktivity	S
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Povalač, Aleš Štohanzl, Milan
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	137099
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/12:PU99568
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Field Programmable Gate Array (FPGA), Ethernet, header, IP, TCP, UDP (en)
http://linked.open.../riv/klicoveSlovo	Ethernet TCP UDP Field Programmable Gate Array (FPGA) header IP
http://linked.open...ontrolniKodProRIV	[4DAB97ABD1D0]
http://linked.open...v/mistoKonaniAkce	Vsetín
http://linked.open...i/riv/mistoVydani	Neuveden
http://linked.open...i/riv/nazevZdroje	Proceedings of the conference Vsacký Cáb 2012
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...UplatneniVysledku	2012
http://linked.open...iv/tvurceVysledku	Povalač, Aleš Štohanzl, Milan
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2012-08-29 (xsd:date)
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Neuveden
https://schema.org/isbn	978-80-214-4579-6
http://localhost/t...ganizacniJednotka	26220
is http://linked.open...avai/riv/vysledek of	FPGA Based 1 Gbps Ethernet Header Detector

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