About: 1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This paper presents a study about the hardware implementation of the TCP/IP and UDP/IP headers compression for the point-to-point communication. The implementation is focused on the achievement of minimum latency and high compression ratio. The applied compression technique is a dictionary-based method. For the TCP/IP, the fixed length of the compressed header was implemented. On the contrary, the variable length of the compressed header was implemented for the UDP/IP. The dictionaries are filled from the original data on both sides. No additional transmissions are used for retaining the continuity of the dictionary content. This paper presents a study about the hardware implementation of the TCP/IP and UDP/IP headers compression for the point-to-point communication. The implementation is focused on the achievement of minimum latency and high compression ratio. The applied compression technique is a dictionary-based method. For the TCP/IP, the fixed length of the compressed header was implemented. On the contrary, the variable length of the compressed header was implemented for the UDP/IP. The dictionaries are filled from the original data on both sides. No additional transmissions are used for retaining the continuity of the dictionary content. (en)
Title	1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA 1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA (en)
skos:prefLabel	1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA 1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA (en)
skos:notation	RIV/00216305:26220/12:PU100472!RIV13-MSM-26220___
http://linked.open...avai/predkladatel	Fakulta elektrotechniky a komunikačních technologií
http://linked.open...avai/riv/aktivita	P S
http://linked.open...avai/riv/aktivity	P(ED2.1.00/03.0072), P(EE2.3.20.0007), P(LD11081), S
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Fedra, Zbyněk Štohanzl, Milan Bobula, Marek
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	183210
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/12:PU100472
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Field Programable Gate Array (FPGA), Ethernet, header, compression, connection, IP, TCP, UDP (en)
http://linked.open.../riv/klicoveSlovo	Field Programable Gate Array (FPGA) compression Ethernet TCP UDP header connection IP
http://linked.open...ontrolniKodProRIV	[B63EE0B603DE]
http://linked.open...v/mistoKonaniAkce	Lisabon
http://linked.open...i/riv/mistoVydani	Neuveden
http://linked.open...i/riv/nazevZdroje	Proceedings of The Seventh International Conference on Systems and Networks Communications, ICSNC 2012
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Wireless communication teams Centre of sensor, information and communication systems Systems of Wireless Internet Communication, SYWIC
http://linked.open...UplatneniVysledku	2012
http://linked.open...iv/tvurceVysledku	Fedra, Zbyněk Štohanzl, Milan Bobula, Marek
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2012-11-18 (xsd:date)
number of pages	7 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Neuveden
https://schema.org/isbn	978-1-61208-231-8
http://localhost/t...ganizacniJednotka	26220
is http://linked.open...avai/riv/vysledek of	1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA

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