About: Combinational Divider in FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Analyzována je možnost syntézy celočíselné kombinační děličky v obvodech FPGA se zřetelem na pokrok v technologii těchto obvodů. Jsou diskutovány tři modely zapsané v jazyku VHDL a porovnány výsledky implementace - spotřeba strukturních prvků a zpoždění, a rovněž omezení bitové šířky. (cs) The possibility of synthesis of combinational divider for unsigned integer numbers in FPGA devices is considered with respect to recent technology development. Three VHDL models are discussed, and corresponding synthesis and implementation results – resource consumption and propagation delay, together with the bit width limitation, are compared. The possibility of synthesis of combinational divider for unsigned integer numbers in FPGA devices is considered with respect to recent technology development. Three VHDL models are discussed, and corresponding synthesis and implementation results – resource consumption and propagation delay, together with the bit width limitation, are compared. (en)
Title	Combinational Divider in FPGA Combinational Divider in FPGA (en) Kombinační dělička v FPGA (cs)
skos:prefLabel	Combinational Divider in FPGA Combinational Divider in FPGA (en) Kombinační dělička v FPGA (cs)
skos:notation	RIV/00216305:26220/07:PU68032!RIV08-GA0-26220___
http://linked.open.../vavai/riv/strany	69-72
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/05/0571), P(GA102/05/0732), Z(MSM0021630513)
http://linked.open...vai/riv/dodaniDat	2008
http://linked.open...aciTvurceVysledku	Kolouch, Jaromír
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	414136
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/07:PU68032
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	arithmetic functions, combinational logic, integer division, synthesis, FPGA, propagation delay, resource consumption (en)
http://linked.open.../riv/klicoveSlovo	propagation delay FPGA arithmetic functions combinational logic integer division resource consumption synthesis
http://linked.open...ontrolniKodProRIV	[A96AB56E0751]
http://linked.open...v/mistoKonaniAkce	Brno
http://linked.open...i/riv/mistoVydani	Brno
http://linked.open...i/riv/nazevZdroje	Proceedings of 17th International Conference Radioelektronika 2007
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	1 (xsd:int)
http://linked.open...vavai/riv/projekt	Methods for Availability Improvement of Free Space Optics Communications Computer modeling and synthesis of digital and mixed analog-digital systems
http://linked.open...UplatneniVysledku	2007
http://linked.open...iv/tvurceVysledku	Kolouch, Jaromír
http://linked.open...vavai/riv/typAkce	CST - Celostátní
http://linked.open.../riv/zahajeniAkce	2007-04-24 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Advanced Electronic Communication Systems and Technologies (ELCOM)
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Vysoké učení technické v Brně
https://schema.org/isbn	1-4244-0821-0
http://localhost/t...ganizacniJednotka	26220
is http://linked.open...avai/riv/vysledek of	Combinational Divider in FPGA Combinational Divider in FPGA Combinational Divider in FPGA

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