About: Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals

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Description	The paper describes a simulation model of a software and hardware recovery circuit. Performance of both models is compared and drawbacks of software recovery are discussed. To model different link conditions, signal source and data path models were created (to model jitter and noise of received signal). All simulations were performed in the Mentor Graphic’s SystemVision 4.4 environment using VHDL-AMS models of signal source, data path and recovery circuits. The software recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design. The paper describes a simulation model of a software and hardware recovery circuit. Performance of both models is compared and drawbacks of software recovery are discussed. To model different link conditions, signal source and data path models were created (to model jitter and noise of received signal). All simulations were performed in the Mentor Graphic’s SystemVision 4.4 environment using VHDL-AMS models of signal source, data path and recovery circuits. The software recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design. (en) Článek se zabývá simulací modelů softwarové a hardwarové obnovy hodinového signálu. Jsou porovnány vlastnosti obou metod a shrnuty jejich výhody a nevýhody. Aby bylo možné modelovat různé podmínky na přenosové trase, byl vytvořen model zdroje datového signálu a digitálního kanálu (lze modelovat jitter i šum přijímaného signálu). Všechny simulace byly provedeny v prostředí SystemVision 4.4 firmy Mentor Graphics pomocí modelů popsaných jazykem VHDL-AMS (zdroj signálu, přenosový kanál a hardwarová obnova dat). Model softwarové obnovy dat byl popsán pomocí syntetizovatelné části jazyka VHDL a může tak být přímo použit jako součást designu pro FPGA. (cs)
Title	Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals (en) Simulace obnovy datového a hodinového signálu ze silně zarušených signálů (cs)
skos:prefLabel	Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals (en) Simulace obnovy datového a hodinového signálu ze silně zarušených signálů (cs)
skos:notation	RIV/00216305:26220/07:PU67574!RIV07-GA0-26220___
http://linked.open.../vavai/riv/strany	211-214
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/05/0571), P(GA102/05/0732), Z(MSM0021630513)
http://linked.open...vai/riv/dodaniDat	2007
http://linked.open...aciTvurceVysledku	Kubíček, Michal
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	449998
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/07:PU67574
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Data Recovery, FPGA, VHDL-AMS, simulation, CDR. (en)
http://linked.open.../riv/klicoveSlovo	FPGA simulation VHDL-AMS CDR. Data Recovery
http://linked.open...ontrolniKodProRIV	[2B8CB3C28C42]
http://linked.open...v/mistoKonaniAkce	Brno
http://linked.open...i/riv/mistoVydani	Department of Radio Electronics, Brno University
http://linked.open...i/riv/nazevZdroje	Proceedings of 17th International Conference Radioelektronika 2007
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	1 (xsd:int)
http://linked.open...vavai/riv/projekt	Methods for Availability Improvement of Free Space Optics Communications Computer modeling and synthesis of digital and mixed analog-digital systems
http://linked.open...UplatneniVysledku	2007
http://linked.open...iv/tvurceVysledku	Kubíček, Michal
http://linked.open...vavai/riv/typAkce	CST - Celostátní
http://linked.open.../riv/zahajeniAkce	2007-04-24 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Advanced Electronic Communication Systems and Technologies (ELCOM)
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	MJ servicsBožetěchova 133, 612 00 Brno, Czech Republic
https://schema.org/isbn	978-80-214-3390-8
http://localhost/t...ganizacniJednotka	26220
is http://linked.open...avai/riv/vysledek of	Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals

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