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  • This paper presents a novel architecture of high-order single-stage sigma-delta (ΣΔ) converter for sensor measurement. The two-step quantization technique was utilized to design of novel architecture of ΣΔ modulator. The time steps are interleaved to achieve resolution improvement without decreasing of conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. This paper describes steps involved in a new VHDL design of a decimation filter for a ΣΔ modulator. Parameters of decimation filter are derived from the specifications of the overall ΣΔ modulator. The proposed architecture of switched-capacitor (SC) ΣΔ modulator was simulated with nonidealities blocks, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages)
  • This paper presents a novel architecture of high-order single-stage sigma-delta (ΣΔ) converter for sensor measurement. The two-step quantization technique was utilized to design of novel architecture of ΣΔ modulator. The time steps are interleaved to achieve resolution improvement without decreasing of conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. This paper describes steps involved in a new VHDL design of a decimation filter for a ΣΔ modulator. Parameters of decimation filter are derived from the specifications of the overall ΣΔ modulator. The proposed architecture of switched-capacitor (SC) ΣΔ modulator was simulated with nonidealities blocks, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages) (en)
Title
  • Modeling and design of novel architecture of multibit switched-capacitor sigma-delta converter with two-step quantization process
  • Modeling and design of novel architecture of multibit switched-capacitor sigma-delta converter with two-step quantization process (en)
skos:prefLabel
  • Modeling and design of novel architecture of multibit switched-capacitor sigma-delta converter with two-step quantization process
  • Modeling and design of novel architecture of multibit switched-capacitor sigma-delta converter with two-step quantization process (en)
skos:notation
  • RIV/00216305:26220/06:PU57572!RIV10-MSM-26220___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/05/0869), P(GD102/03/H105), Z(MSM0021630503)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 486144
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26220/06:PU57572
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • sigma-delta modulation, decimation filter, analog-to -digital conversion (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [AF3104BFA13C]
http://linked.open...v/mistoKonaniAkce
  • Morne
http://linked.open...i/riv/mistoVydani
  • NEUVEDEN
http://linked.open...i/riv/nazevZdroje
  • The International Conference on Systems, IEEE Computer Society
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Fujcik, Lukáš
  • Háze, Jiří
  • Vrba, Radimír
  • Mougel, Thibault
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • Morne, Mauritius
https://schema.org/isbn
  • 0-7695-2540-7
http://localhost/t...ganizacniJednotka
  • 26220
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