About: New VHDL Design of Decimation Filter for Sigma-Delta Modulator     Goto   Sponge   NotDistinct   Permalink

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Description
  • Článek popisuje potřebné kroky při návrhu decimačního filtru pro sigma-delta modulátor. Návrh byl prováděn pomocí nástrojů Matlab a MathCad.Pro výsledný návrh byl použit jazyk VHDL a pak byl implementován do obvodu FPGA Spartan-3. (cs)
  • This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta (ΣΔ) modulator. Parameters of decimation filter are derived from the specifications of the overall ΣΔ modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Then second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 µm technology.
  • This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta (ΣΔ) modulator. Parameters of decimation filter are derived from the specifications of the overall ΣΔ modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Then second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 µm technology. (en)
Title
  • New VHDL Design of Decimation Filter for Sigma-Delta Modulator
  • Návrh decimačního filtru pro sigma-delta modulátor pomocí VHDL (cs)
  • New VHDL Design of Decimation Filter for Sigma-Delta Modulator (en)
skos:prefLabel
  • New VHDL Design of Decimation Filter for Sigma-Delta Modulator
  • Návrh decimačního filtru pro sigma-delta modulátor pomocí VHDL (cs)
  • New VHDL Design of Decimation Filter for Sigma-Delta Modulator (en)
skos:notation
  • RIV/00216305:26220/05:PU51430!RIV07-GA0-26220___
http://linked.open.../vavai/riv/strany
  • 32-35
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/05/0869), P(GD102/03/H105), Z(MSM0021630503)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 532794
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26220/05:PU51430
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • sigma-delta modulation, decimation filter, VHDL (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [D2332C0FFD1E]
http://linked.open...v/mistoKonaniAkce
  • Kuala Lumpur
http://linked.open...i/riv/mistoVydani
  • Kuala Lumpur, Malaysie
http://linked.open...i/riv/nazevZdroje
  • International Conference on Sesnsor and New Techniques in Pharmaceutical and Biomedical Research
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Fujcik, Lukáš
  • Vrba, Radimír
  • Mougel, Thibault
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • Malaysia
https://schema.org/isbn
  • 0-7803-9371-6
http://localhost/t...ganizacniJednotka
  • 26220
is http://linked.open...avai/riv/vysledek of
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