About: Analytic Approach to RTL Testability Analysis

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The paper deals with analytical approach to the RTL testability analysis and its results. Approach is based as on circuit i path analysis, finding i paths existence conditions and the ways in which these conditions could be set, as on difficult to control/observe nodes location. On these testability analysis results basis, UUA (Unit Under Analysis) modification is suggested. This modification is based on insertion of selected registers into scan chain in order to improve controllability/observability pproperties of previously located difficult to control/observe nodes. The goal of presented methodology is to maximally utilise current UUA structure for future test application to reduce necessary modifications for UUA testability improvements suggested by UUA testability analysis results. The paper deals with analytical approach to the RTL testability analysis and its results. Approach is based as on circuit i path analysis, finding i paths existence conditions and the ways in which these conditions could be set, as on difficult to control/observe nodes location. On these testability analysis results basis, UUA (Unit Under Analysis) modification is suggested. This modification is based on insertion of selected registers into scan chain in order to improve controllability/observability pproperties of previously located difficult to control/observe nodes. The goal of presented methodology is to maximally utilise current UUA structure for future test application to reduce necessary modifications for UUA testability improvements suggested by UUA testability analysis results. (en)
Title	Analytic Approach to RTL Testability Analysis Analytic Approach to RTL Testability Analysis (en)
skos:prefLabel	Analytic Approach to RTL Testability Analysis Analytic Approach to RTL Testability Analysis (en)
skos:notation	RIV/00216305:26220/01:PU28712!RIV/2002/GA0/262202/N
http://linked.open.../vavai/riv/strany	363-367
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(GA102/01/1531)
http://linked.open...vai/riv/dodaniDat	2002
http://linked.open...aciTvurceVysledku	Kotásek, Zdeněk Strnadel, Josef
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	673156
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/01:PU28712
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	testability analysis, controllability, observability, scan chain, scan register, unit under analysis (en)
http://linked.open.../riv/klicoveSlovo	controllability scan chain observability testability analysis scan register unit under analysis
http://linked.open...ontrolniKodProRIV	[9E2D1383967A]
http://linked.open...v/mistoKonaniAkce	Brno
http://linked.open...i/riv/mistoVydani	Brno
http://linked.open...i/riv/nazevZdroje	Proceedings of 7th Conference Student FEI 2001
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...ocetUcastnikuAkce	0 (xsd:int)
http://linked.open...nichUcastnikuAkce	0 (xsd:int)
http://linked.open...vavai/riv/projekt	Formal approaches in digital circuit diagnostics - testable design verification
http://linked.open...UplatneniVysledku	2001
http://linked.open...iv/tvurceVysledku	Kotásek, Zdeněk Strnadel, Josef
http://linked.open...vavai/riv/typAkce	CST - Celostátní
http://linked.open.../riv/zahajeniAkce	2001-04-03 (xsd:date)
number of pages	5 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Vysoké učení technické v Brně
https://schema.org/isbn	80-214-1860-5
http://localhost/t...ganizacniJednotka	26220

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