About: Formal Verification of a FIFO Component in Design of Network Monitoring Hardware

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The paper presents our approach of using a formal verification method, the model checking, to verify whether a particular component of hardware design matches its specification. We have applied this approach in the Liberouter project, which is aimed to develop an FPGA based high-speed network monitoring and routing hardware. In the paper, we focus on a FIFO component - the process of its verification, detected errors, and the way of their correction. The paper presents our approach of using a formal verification method, the model checking, to verify whether a particular component of hardware design matches its specification. We have applied this approach in the Liberouter project, which is aimed to develop an FPGA based high-speed network monitoring and routing hardware. In the paper, we focus on a FIFO component - the process of its verification, detected errors, and the way of their correction. (en)
Title	Formal Verification of a FIFO Component in Design of Network Monitoring Hardware Formal Verification of a FIFO Component in Design of Network Monitoring Hardware (en)
skos:prefLabel	Formal Verification of a FIFO Component in Design of Network Monitoring Hardware Formal Verification of a FIFO Component in Design of Network Monitoring Hardware (en)
skos:notation	RIV/00216224:14330/06:00015311!RIV11-AV0-14330___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(1ET408050503), P(1M0545), P(GA201/03/0509), P(GD102/05/H050), Z(MSM0021622419)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Šafránek, David Kratochvíla, Tomáš Řehák, Vojtěch
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Masarykova univerzita / Fakulta informatiky
http://linked.open...dnocenehoVysledku	476158
http://linked.open...ai/riv/idVysledku	RIV/00216224:14330/06:00015311
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	formal verification; model checking; component-based hardware; FPGA (en)
http://linked.open.../riv/klicoveSlovo	FPGA model checking component-based hardware formal verification
http://linked.open...ontrolniKodProRIV	[0424B73A1A94]
http://linked.open...v/mistoKonaniAkce	Praha
http://linked.open...i/riv/mistoVydani	Praha
http://linked.open...i/riv/nazevZdroje	10 years of CESNET - CESNET CONFERENCE 2006
http://linked.open...in/vavai/riv/obor	IN
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Institute for Theoretical Computer Science Integrated Approach to Education of PhD Students in the Area of Parallel and Distributed Systems Automated Verification of Parallel and Distributed Systems Techniques for automatic verification and validation of software and hardware systems
http://linked.open...UplatneniVysledku	2006
http://linked.open...iv/tvurceVysledku	Šafránek, David Řehák, Vojtěch Kratochvíla, Tomáš
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open...ain/vavai/riv/wos	000271027200015
http://linked.open.../riv/zahajeniAkce	2006-01-01 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Highly Parallel and Distributed Computing Systems
number of pages	10 (xsd:int)
http://purl.org/ne...btex#hasPublisher	CESNET, z.s.p.o.
https://schema.org/isbn	978-80-239-6533-9
http://localhost/t...ganizacniJednotka	14330
is http://linked.open...avai/riv/vysledek of	Formal Verification of a FIFO Component in Design of Network Monitoring Hardware

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