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Description
  • Although important from software performance perspective, the behavior of memory caches is not captured by the common approaches to modeling of software performance, where the software performance models tend to treat operation durations as constants despite the fact that the operations compete for memory caches. Incorporating memory cache models into software performance models is hindered by the fact that existing cache models do not provide information about timings and penalties, but only about hits and misses. The paper outlines the relationship of cache events and cache timings on a real computer architecture, indicating that the existing practice of modeling cache miss penalties as constants is not sufficient to model software performance faithfully.
  • Although important from software performance perspective, the behavior of memory caches is not captured by the common approaches to modeling of software performance, where the software performance models tend to treat operation durations as constants despite the fact that the operations compete for memory caches. Incorporating memory cache models into software performance models is hindered by the fact that existing cache models do not provide information about timings and penalties, but only about hits and misses. The paper outlines the relationship of cache events and cache timings on a real computer architecture, indicating that the existing practice of modeling cache miss penalties as constants is not sufficient to model software performance faithfully. (en)
Title
  • Timing Penalties Associated with Cache Sharing
  • Timing Penalties Associated with Cache Sharing (en)
skos:prefLabel
  • Timing Penalties Associated with Cache Sharing
  • Timing Penalties Associated with Cache Sharing (en)
skos:notation
  • RIV/00216208:11320/09:10005300!RIV11-GA0-11320___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(7E08004), P(GD201/09/H057), Z(MSM0021620838)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 346379
http://linked.open...ai/riv/idVysledku
  • RIV/00216208:11320/09:10005300
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • resource sharing; performance modeling; processor caches (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [041CA1688E08]
http://linked.open...v/mistoKonaniAkce
  • London, UK
http://linked.open...i/riv/mistoVydani
  • NEW YORK, NY
http://linked.open...i/riv/nazevZdroje
  • 2009 IEEE International Symposium on Modeling, Analysis & Simulation of Computer and Telecommunication Systems (MASCOTS)
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Babka, Vlastimil
  • Tůma, Petr
  • Libič, Peter
http://linked.open...vavai/riv/typAkce
http://linked.open...ain/vavai/riv/wos
  • 000275140200059
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
issn
  • 1526-7539
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE
https://schema.org/isbn
  • 978-1-4244-4926-2
http://localhost/t...ganizacniJednotka
  • 11320
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