About: Low noise programmable PLL for precise timing systems

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Low noise programmable phase-locked loop (PLL) is suitable for timing applications serving as system clock. With long term stable reference such as GNSS disciplined oscillator, the PLL provides both long and short term stable frequency. The device accepts 5MHz or 10MHz sine waves typical for long term stable references. Output frequency can be programmed within the interval of 100MHz to 350MHz, which is convenient source clock frequency for high precision timing systems. Programmable output gain and frequency is set via either an UART interface with TTL levels or USB CDC emulating standard serial port. Output signal peak-to-peak amplitude can be set to values of 350mV to 1V into 50 ohms. Phase stability with respect to temperature changes is in the interval of 60°C to 70°C below +-1ps/K. Low noise programmable phase-locked loop (PLL) is suitable for timing applications serving as system clock. With long term stable reference such as GNSS disciplined oscillator, the PLL provides both long and short term stable frequency. The device accepts 5MHz or 10MHz sine waves typical for long term stable references. Output frequency can be programmed within the interval of 100MHz to 350MHz, which is convenient source clock frequency for high precision timing systems. Programmable output gain and frequency is set via either an UART interface with TTL levels or USB CDC emulating standard serial port. Output signal peak-to-peak amplitude can be set to values of 350mV to 1V into 50 ohms. Phase stability with respect to temperature changes is in the interval of 60°C to 70°C below +-1ps/K. (en)
Title	Low noise programmable PLL for precise timing systems Low noise programmable PLL for precise timing systems (en)
skos:prefLabel	Low noise programmable PLL for precise timing systems Low noise programmable PLL for precise timing systems (en)
skos:notation	RIV/68407700:21340/12:00204166!RIV13-MSM-21340___
http://linked.open...avai/riv/aktivita	I
http://linked.open...avai/riv/aktivity	I
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Kodet, Jan Procházka, Ivan Michálek, Vojtěch
http://linked.open.../riv/druhVysledku	G/B - Funkční vzorek
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...onomickeParametry	50000,- Kč
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta jaderná a fyzikálně inženýrská
http://linked.open...dnocenehoVysledku	147500
http://linked.open...ai/riv/idVysledku	RIV/68407700:21340/12:00204166
http://linked.open...terniIdentifikace	14112-12-zavesprg-Mich
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open...vai/riv/kategorie	A - Do 5 mil. Kč
http://linked.open.../riv/klicovaSlova	phase-locked loop; precise timing (en)
http://linked.open.../riv/klicoveSlovo	phase-locked loop precise timing
http://linked.open...ontrolniKodProRIV	[4B18A61BF888]
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...UplatneniVysledku	2012
http://linked.open...echnickeParametry	intput 5 or 10MHz; output progr. 100-350 MHz / 350-1000 mV; temp. stab. below 1ps/K 60-70 °C; table-top size
http://linked.open...iv/tvurceVysledku	Kodet, Jan Procházka, Ivan Michálek, Vojtěch
http://linked.open...avai/riv/vlastnik	ČVUT FJFI
http://linked.open...itiJinymSubjektem	N - Nabytí licence není nutné (výsledek není licencován)
http://localhost/t...ganizacniJednotka	21340

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