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  • The paper describes an ASIC implementation of a linear congruence solver, part of a parallel system for solution of linear equations, and presents synthesis results for three different standard cell libraries. The previous VHDL design was adapted to three ASIC technologies (130 nm, 110 nm, and 55 nm) from two different vendors and the synthesized results were mutually compared. The comparison results were further used to obtain a view of design properties in higher density technologies.
  • The paper describes an ASIC implementation of a linear congruence solver, part of a parallel system for solution of linear equations, and presents synthesis results for three different standard cell libraries. The previous VHDL design was adapted to three ASIC technologies (130 nm, 110 nm, and 55 nm) from two different vendors and the synthesized results were mutually compared. The comparison results were further used to obtain a view of design properties in higher density technologies. (en)
Title
  • An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries
  • An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries (en)
skos:prefLabel
  • An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries
  • An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries (en)
skos:notation
  • RIV/68407700:21240/14:00224305!RIV15-GA0-21240___
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  • P(GAP103/12/2377)
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  • 2426
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  • RIV/68407700:21240/14:00224305
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  • system of linear equations; system of linear congruences; residue number system; error-free computation; ASIC; System on Chip (en)
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  • [AA7B26850639]
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  • Marseille
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  • Monterey
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  • Proceedings of the 21st IEEE International Conference on Electronics Circuits and Systems
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  • Buček, Jiří
  • Kubalík, Pavel
  • Lórencz, Róbert
  • Zahradnický, Tomáš
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number of pages
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  • 10.1109/ICECS.2014.7050083
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  • IEEE Circuits and Systems Society
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  • 978-1-4799-4243-5
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  • 21240
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