About: System on Chip Design of a Linear System Solver

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This paper is focused on hardware error-free solution of dense linear systems using residual arithmetic on a System on Chip Modular System. The designed Modular System uses Residual Processors (RP)s for solving independent linear systems in residue arithmetic and combines RP solutions into solution of the linear system. A System on Chip architecture of the Modular System with several RPs is designed, each with a large memory unit used for data transfer and storage. A Xilinx FPGA architecture with a MicroBlaze processor is used to verify the proposed architecture. The experimental results are obtained for an evaluation FPGA board with Virtex 6 and a 1GiB DDR memory and serve for further theoretical analysis of the system performance for various linear system sizes and the architecture of the system. This paper is focused on hardware error-free solution of dense linear systems using residual arithmetic on a System on Chip Modular System. The designed Modular System uses Residual Processors (RP)s for solving independent linear systems in residue arithmetic and combines RP solutions into solution of the linear system. A System on Chip architecture of the Modular System with several RPs is designed, each with a large memory unit used for data transfer and storage. A Xilinx FPGA architecture with a MicroBlaze processor is used to verify the proposed architecture. The experimental results are obtained for an evaluation FPGA board with Virtex 6 and a 1GiB DDR memory and serve for further theoretical analysis of the system performance for various linear system sizes and the architecture of the system. (en)
Title	System on Chip Design of a Linear System Solver System on Chip Design of a Linear System Solver (en)
skos:prefLabel	System on Chip Design of a Linear System Solver System on Chip Design of a Linear System Solver (en)
skos:notation	RIV/68407700:21240/14:00224196!RIV15-GA0-21240___
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(GAP103/12/2377)
http://linked.open...vai/riv/dodaniDat	2015
http://linked.open...aciTvurceVysledku	Buček, Jiří Kubalík, Pavel Zahradnický, Tomáš Lórencz, Róbert
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	49141
http://linked.open...ai/riv/idVysledku	RIV/68407700:21240/14:00224196
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	system of linear equations; system of linear congruences; residue number system; error-free computation; FPGA; System on Chip (en)
http://linked.open.../riv/klicoveSlovo	FPGA error-free computation system of linear congruences residue number system System on Chip system of linear equations
http://linked.open...ontrolniKodProRIV	[0822D6C80864]
http://linked.open...v/mistoKonaniAkce	Tampere
http://linked.open...i/riv/mistoVydani	Piscataway
http://linked.open...i/riv/nazevZdroje	2014 International Symposium on System-on-Chip Proceedings
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	4 (xsd:int)
http://linked.open...cetTvurcuVysledku	4 (xsd:int)
http://linked.open...vavai/riv/projekt	Study of properties of residual arithmetic for solving sets of linear equations
http://linked.open...UplatneniVysledku	2014
http://linked.open...iv/tvurceVysledku	Buček, Jiří Kubalík, Pavel Lórencz, Róbert Zahradnický, Tomáš
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2014-10-28 (xsd:date)
number of pages	6 (xsd:int)
http://bibframe.org/vocab/doi	10.1109/ISSOC.2014.6972445
http://purl.org/ne...btex#hasPublisher	IEEE
https://schema.org/isbn	978-1-4799-6889-3
http://localhost/t...ganizacniJednotka	21240

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