About: Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver

Facets (new session)
Description
Metadata
Settings
- owl:sameAs
- Inference Rule:

About: Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver Goto Sponge NotDistinct Permalink

An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Residual processor (RP) is a dedicated hardware for solution of sets of linear congruences. RPs are parts of a larger modular system for error-free solution of linear equations in residue arithmetic. We present new FPGA and ASIC RP implementations, focusing mainly on their memory units being a bottleneck of the calculation and therefore determining the efficiency of the system. First, we choose an FPGA to easily test the functionality of our implementation, then we do the same in ASIC, and finally we compare both implementations together. The experimental FPGA results are obtained for Xilinx Virtex 6, while the ASIC results are obtained from Synopsys tools with a 130 nm standard cell library. Results also present a maximum matrix dimension fitting directly into the FPGA and achieved speed as a function of the dimension. Residual processor (RP) is a dedicated hardware for solution of sets of linear congruences. RPs are parts of a larger modular system for error-free solution of linear equations in residue arithmetic. We present new FPGA and ASIC RP implementations, focusing mainly on their memory units being a bottleneck of the calculation and therefore determining the efficiency of the system. First, we choose an FPGA to easily test the functionality of our implementation, then we do the same in ASIC, and finally we compare both implementations together. The experimental FPGA results are obtained for Xilinx Virtex 6, while the ASIC results are obtained from Synopsys tools with a 130 nm standard cell library. Results also present a maximum matrix dimension fitting directly into the FPGA and achieved speed as a function of the dimension. (en)
Title	Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver (en)
skos:prefLabel	Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver (en)
skos:notation	RIV/68407700:21240/13:00209154!RIV14-GA0-21240___
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(GAP103/12/2377)
http://linked.open...vai/riv/dodaniDat	2014
http://linked.open...aciTvurceVysledku	Buček, Jiří Kubalík, Pavel Zahradnický, Tomáš Lórencz, Róbert
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	66209
http://linked.open...ai/riv/idVysledku	RIV/68407700:21240/13:00209154
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	system of linear equations; residue number system; error-free computation; FPGA; ASIC (en)
http://linked.open.../riv/klicoveSlovo	FPGA error-free computation residue number system system of linear equations ASIC
http://linked.open...ontrolniKodProRIV	[EEA30EBFA004]
http://linked.open...v/mistoKonaniAkce	Santander
http://linked.open...i/riv/mistoVydani	Piscataway
http://linked.open...i/riv/nazevZdroje	Proceedings of 16th Euromicro Conference on Digital System Design
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	4 (xsd:int)
http://linked.open...cetTvurcuVysledku	4 (xsd:int)
http://linked.open...vavai/riv/projekt	Study of properties of residual arithmetic for solving sets of linear equations
http://linked.open...UplatneniVysledku	2013
http://linked.open...iv/tvurceVysledku	Buček, Jiří Kubalík, Pavel Lórencz, Róbert Zahradnický, Tomáš
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2013-09-04 (xsd:date)
number of pages	4 (xsd:int)
http://bibframe.org/vocab/doi	10.1109/DSD.2013.125
http://purl.org/ne...btex#hasPublisher	IEEE Service Center
https://schema.org/isbn	978-0-7695-5074-9
http://localhost/t...ganizacniJednotka	21240

Faceted Search & Find service v1.16.118 as of Jun 21 2024

Alternative Linked Data Documents: ODE Content Formats:

RDF

ODATA

Microdata

About

OpenLink Virtuoso version 07.20.3240 as of Jun 21 2024, on Linux (x86_64-pc-linux-gnu), Single-Server Edition (126 GB total memory, 77 GB memory in use)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2024 OpenLink Software