About: Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The residual processor is a dedicated hardware for solving sets of linear congruences. It is a part of the modular system for solving sets of linear equations without rounding errors using Residue Number System. We present a new FPGA implementation of the residual processor, focusing mainly on the memory unit that forms a bottleneck of the calculation, and therefore determines the effectivity of the system. FPGA has been chosen, as it allows us to optimally implement the designed architecture depending on the size of the problem. The proposed memory architecture of the modular system is implemented using the internal FPGA block RAM. Experimental results are obtained for the Xilinx Virtex 6 family. Results present the maximum matrix dimension fitting directly into the FPGA, and achieved speed as a function of the dimension. The residual processor is a dedicated hardware for solving sets of linear congruences. It is a part of the modular system for solving sets of linear equations without rounding errors using Residue Number System. We present a new FPGA implementation of the residual processor, focusing mainly on the memory unit that forms a bottleneck of the calculation, and therefore determines the effectivity of the system. FPGA has been chosen, as it allows us to optimally implement the designed architecture depending on the size of the problem. The proposed memory architecture of the modular system is implemented using the internal FPGA block RAM. Experimental results are obtained for the Xilinx Virtex 6 family. Results present the maximum matrix dimension fitting directly into the FPGA, and achieved speed as a function of the dimension. (en)
Title	Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA (en)
skos:prefLabel	Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA (en)
skos:notation	RIV/68407700:21240/12:00197211!RIV14-MSM-21240___
http://linked.open...avai/riv/aktivita	I P
http://linked.open...avai/riv/aktivity	I, P(GAP103/12/2377)
http://linked.open...vai/riv/dodaniDat	2014
http://linked.open...aciTvurceVysledku	Buček, Jiří Kubalík, Pavel Zahradnický, Tomáš Lórencz, Róbert
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	129806
http://linked.open...ai/riv/idVysledku	RIV/68407700:21240/12:00197211
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	linear systems; system of linear congruences; solver; FPGA (en)
http://linked.open.../riv/klicoveSlovo	FPGA system of linear congruences linear systems solver
http://linked.open...ontrolniKodProRIV	[51410F0BC368]
http://linked.open...v/mistoKonaniAkce	Seville
http://linked.open...i/riv/mistoVydani	Monterey
http://linked.open...i/riv/nazevZdroje	The 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
http://linked.open...in/vavai/riv/obor	IN
http://linked.open...ichTvurcuVysledku	4 (xsd:int)
http://linked.open...cetTvurcuVysledku	4 (xsd:int)
http://linked.open...vavai/riv/projekt	Study of properties of residual arithmetic for solving sets of linear equations
http://linked.open...UplatneniVysledku	2012
http://linked.open...iv/tvurceVysledku	Buček, Jiří Kubalík, Pavel Lórencz, Róbert Zahradnický, Tomáš
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2012-12-09 (xsd:date)
number of pages	4 (xsd:int)
http://bibframe.org/vocab/doi	10.1109/ICECS.2012.6463632
http://purl.org/ne...btex#hasPublisher	IEEE Circuits and Systems Society
https://schema.org/isbn	978-1-4673-1261-5
http://localhost/t...ganizacniJednotka	21240

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