About: Fault Models Usability Study for On-line Tested FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	FPGAs are susceptible to many environment effects that can cause soft errors (errors which can be corrected by the reconfiguration ability of the FPGA). Two different fault models are discussed and compared in this paper. The first one - Stuck-at model - is widely used in many applications and it is not limited to the FPGAs. The second one - Bit-flip model - can affect SRAM cells that are used to configure the internal routing of the FPGA and to set up the behavior of the Look-Up Tables (LUTs). The change of the LUT behavior is the only Bit-flip effect considered in this paper. A fault model analysis has been performed on small example designs in order to find the differences between the fault models. This paper discusses the relevance of using two types of models Stuck-at and Bit-flip with respect to the dependability characteristics Fault Security (FS) and Self-Testing (ST). The fault simulation using both fault models has been performed to verify the analysis FPGAs are susceptible to many environment effects that can cause soft errors (errors which can be corrected by the reconfiguration ability of the FPGA). Two different fault models are discussed and compared in this paper. The first one - Stuck-at model - is widely used in many applications and it is not limited to the FPGAs. The second one - Bit-flip model - can affect SRAM cells that are used to configure the internal routing of the FPGA and to set up the behavior of the Look-Up Tables (LUTs). The change of the LUT behavior is the only Bit-flip effect considered in this paper. A fault model analysis has been performed on small example designs in order to find the differences between the fault models. This paper discusses the relevance of using two types of models Stuck-at and Bit-flip with respect to the dependability characteristics Fault Security (FS) and Self-Testing (ST). The fault simulation using both fault models has been performed to verify the analysis (en)
Title	Fault Models Usability Study for On-line Tested FPGA Fault Models Usability Study for On-line Tested FPGA (en)
skos:prefLabel	Fault Models Usability Study for On-line Tested FPGA Fault Models Usability Study for On-line Tested FPGA (en)
skos:notation	RIV/68407700:21240/11:00182599!RIV12-MSM-21240___
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(GA102/09/1668), S, Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat	2012
http://linked.open...aciTvurceVysledku	Kohlík, Martin Borecký, Jaroslav Kubátová, Hana Kubalík, Pavel
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	199424
http://linked.open...ai/riv/idVysledku	RIV/68407700:21240/11:00182599
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	FPGA; fault model; Bit-flip; Stuck-at; fault simulation (en)
http://linked.open.../riv/klicoveSlovo	Bit-flip Stuck-at fault model fault simulation FPGA
http://linked.open...ontrolniKodProRIV	[A62CBD96FE1D]
http://linked.open...v/mistoKonaniAkce	Oulu
http://linked.open...i/riv/mistoVydani	Los Alamitos
http://linked.open...i/riv/nazevZdroje	Proceedings of the 14th Euromicro Conference on Digital System Design
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	4 (xsd:int)
http://linked.open...cetTvurcuVysledku	4 (xsd:int)
http://linked.open...vavai/riv/projekt	SoC circuits reliability and availability improvement
http://linked.open...UplatneniVysledku	2011
http://linked.open...iv/tvurceVysledku	Kubátová, Hana Borecký, Jaroslav Kohlík, Martin Kubalík, Pavel
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2011-08-31 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum perspektivních informačních a komunikačních technologií
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society Press
https://schema.org/isbn	978-0-7695-4494-6
http://localhost/t...ganizacniJednotka	21240

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