About: Dependable Interconnection of Dependable Blocks

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This paper presents future work, which the main goal is to find a solution for interconection between reconfigurable blocks and keep fault secure parameters. Described method will use a partial reconfiguration to obtain self-repair ability. Our concept will be proved on a practical problem, which is implementing the railway station system in the FPGA. This paper presents future work, which the main goal is to find a solution for interconection between reconfigurable blocks and keep fault secure parameters. Described method will use a partial reconfiguration to obtain self-repair ability. Our concept will be proved on a practical problem, which is implementing the railway station system in the FPGA. (en)
Title	Dependable Interconnection of Dependable Blocks Dependable Interconnection of Dependable Blocks (en)
skos:prefLabel	Dependable Interconnection of Dependable Blocks Dependable Interconnection of Dependable Blocks (en)
skos:notation	RIV/68407700:21240/10:00169353!RIV11-GA0-21240___
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(GA102/09/1668), S, Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Borecký, Jaroslav Kubátová, Hana
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	253325
http://linked.open...ai/riv/idVysledku	RIV/68407700:21240/10:00169353
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	SEU; Fault Tolerant; FPGA; partial reconfiguration (en)
http://linked.open.../riv/klicoveSlovo	SEU FPGA Fault Tolerant partial reconfiguration
http://linked.open...ontrolniKodProRIV	[5002A950FF11]
http://linked.open...v/mistoKonaniAkce	Lille
http://linked.open...i/riv/mistoVydani	Linz
http://linked.open...i/riv/nazevZdroje	Proceedings of the Work in Progress Session SEAA 2010 and DSD 2010
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	SoC circuits reliability and availability improvement
http://linked.open...UplatneniVysledku	2010
http://linked.open...iv/tvurceVysledku	Kubátová, Hana Borecký, Jaroslav
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2010-09-01 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum perspektivních informačních a komunikačních technologií
number of pages	2 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Johannes Kepler University
https://schema.org/isbn	978-3-902457-27-1
http://localhost/t...ganizacniJednotka	21240

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