About: Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints

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About: Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints Goto Sponge NotDistinct Permalink

An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementation of the functional and completion detection logics, what simplifies the design process; 3) circuit output latency is based on the actual gate delays of the unbounded nature; 4) absence of additional synchronization chains (even of a local nature). However, the area and speed penalty is rather high. In contrast to the state-of-the-art approaches, where simple (NAND, NOR, etc.) 2 input gates are used, we propose a synthesis method based on complex nodes, i.e., nodes implementing any function of an arbitrary number of inputs. Synchronous synthesis procedures may be freely adopted for this purpose. Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementation of the functional and completion detection logics, what simplifies the design process; 3) circuit output latency is based on the actual gate delays of the unbounded nature; 4) absence of additional synchronization chains (even of a local nature). However, the area and speed penalty is rather high. In contrast to the state-of-the-art approaches, where simple (NAND, NOR, etc.) 2 input gates are used, we propose a synthesis method based on complex nodes, i.e., nodes implementing any function of an arbitrary number of inputs. Synchronous synthesis procedures may be freely adopted for this purpose. (en)
Title	Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints (en)
skos:prefLabel	Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints (en)
skos:notation	RIV/68407700:21240/10:00169329!RIV11-GA0-21240___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/09/1668), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Fišer, Petr
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	247706
http://linked.open...ai/riv/idVysledku	RIV/68407700:21240/10:00169329
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	asynchronous circuits, DIMS, direct logic, NCL (en)
http://linked.open.../riv/klicoveSlovo	DIMS NCL asynchronous circuits direct logic
http://linked.open...ontrolniKodProRIV	[71AF075FFC47]
http://linked.open...v/mistoKonaniAkce	Lille
http://linked.open...i/riv/mistoVydani	Los Alamitos
http://linked.open...i/riv/nazevZdroje	Proceedings of the 13th Euromicro Conference on Digital System Design
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	SoC circuits reliability and availability improvement
http://linked.open...UplatneniVysledku	2010
http://linked.open...iv/tvurceVysledku	Fišer, Petr Lemberski, I.
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2010-09-01 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum perspektivních informačních a komunikačních technologií
number of pages	8 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society Press
https://schema.org/isbn	978-0-7695-4171-6
http://localhost/t...ganizacniJednotka	21240

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