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| Description
| - Memory controller design is challenging as realtime embedded systems feature an increasing diversity of realtime and non-real-time applications with variable transaction sizes. To satisfy the requirements of the applications, tight bounds on the worst-case execution time (WCET) of memory transactions must be provided to real-time applications, while the lowest possible average execution time must be given to the rest. Existing real-time memory controllers cannot efficiently achieve this goal as they either bound the WCET by sacrificing the average execution time, or are not scalable to directly support variable transaction sizes, or both. In this paper, we propose to use dynamic command scheduling, which is capable of efficiently dealing with transactions with variable sizes. The three main contributions of this paper are: 1) a back-end architecture for a real-time memory controller with a dynamic command scheduling algorithm, 2) a formalization of the timings of the memory transactions for the proposed architecture and algorithm, and 3) two techniques to bound the WCET of transactions with both fixed and variable sizes, respectively. We experimentally evaluate the proposed memory controller and compare both the worst-case and average-case execution times of transactions to a state-of-the-art semi-static approach. The results demonstrate that dynamic command scheduling outperforms the semi-static approach by 33.4% in the average case and performs at least equally well in the worst case. We also show the WCET is tight for transactions with fixed and variable sizes, respectively.
- Memory controller design is challenging as realtime embedded systems feature an increasing diversity of realtime and non-real-time applications with variable transaction sizes. To satisfy the requirements of the applications, tight bounds on the worst-case execution time (WCET) of memory transactions must be provided to real-time applications, while the lowest possible average execution time must be given to the rest. Existing real-time memory controllers cannot efficiently achieve this goal as they either bound the WCET by sacrificing the average execution time, or are not scalable to directly support variable transaction sizes, or both. In this paper, we propose to use dynamic command scheduling, which is capable of efficiently dealing with transactions with variable sizes. The three main contributions of this paper are: 1) a back-end architecture for a real-time memory controller with a dynamic command scheduling algorithm, 2) a formalization of the timings of the memory transactions for the proposed architecture and algorithm, and 3) two techniques to bound the WCET of transactions with both fixed and variable sizes, respectively. We experimentally evaluate the proposed memory controller and compare both the worst-case and average-case execution times of transactions to a state-of-the-art semi-static approach. The results demonstrate that dynamic command scheduling outperforms the semi-static approach by 33.4% in the average case and performs at least equally well in the worst case. We also show the WCET is tight for transactions with fixed and variable sizes, respectively. (en)
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| Title
| - Dynamic Command Scheduling for Real-Time Memory Controllers
- Dynamic Command Scheduling for Real-Time Memory Controllers (en)
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| skos:prefLabel
| - Dynamic Command Scheduling for Real-Time Memory Controllers
- Dynamic Command Scheduling for Real-Time Memory Controllers (en)
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| skos:notation
| - RIV/68407700:21230/14:00221846!RIV15-MSM-21230___
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| http://linked.open...avai/riv/aktivita
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| http://linked.open...avai/riv/aktivity
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| http://linked.open...vai/riv/dodaniDat
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| http://linked.open...aciTvurceVysledku
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| http://linked.open.../riv/druhVysledku
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| http://linked.open...iv/duvernostUdaju
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| http://linked.open...titaPredkladatele
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| http://linked.open...dnocenehoVysledku
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| http://linked.open...ai/riv/idVysledku
| - RIV/68407700:21230/14:00221846
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| http://linked.open...riv/jazykVysledku
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| http://linked.open.../riv/klicovaSlova
| - Bismuth; Dynamic scheduling; Heuristic algorithms; Memory management; Real-time systems; SDRAM; Timing (en)
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| http://linked.open.../riv/klicoveSlovo
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| http://linked.open...ontrolniKodProRIV
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| http://linked.open...v/mistoKonaniAkce
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| http://linked.open...i/riv/mistoVydani
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| http://linked.open...i/riv/nazevZdroje
| - Proceedings of the 26th Euromicro Conference on Real-Time Systems (ECRTS)
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| http://linked.open...in/vavai/riv/obor
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| http://linked.open...ichTvurcuVysledku
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| http://linked.open...cetTvurcuVysledku
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| http://linked.open...vavai/riv/projekt
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| http://linked.open...UplatneniVysledku
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| http://linked.open...iv/tvurceVysledku
| - Li, Y.
- Akesson, Benny
- Goossens, K.
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| http://linked.open...vavai/riv/typAkce
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| http://linked.open...ain/vavai/riv/wos
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| http://linked.open.../riv/zahajeniAkce
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| issn
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| number of pages
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| http://bibframe.org/vocab/doi
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| http://purl.org/ne...btex#hasPublisher
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| https://schema.org/isbn
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| http://localhost/t...ganizacniJednotka
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