About: Experience in Virtual Testing of RSD Cyclic A/D converters

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This paper deals with the ADC non-linearity extraction using a newly developed Virtual Testing Environment (VTE). The VTE proposed is built on Verilog-A implementation of the Servo-Loop unit fully integrated into Cadence design environment. The Servo-Loop method used is aimed at the non-linearity extraction of static ADC transfer curve; in this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. Powerful capabilities of the proposed VTE were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre. This paper deals with the ADC non-linearity extraction using a newly developed Virtual Testing Environment (VTE). The VTE proposed is built on Verilog-A implementation of the Servo-Loop unit fully integrated into Cadence design environment. The Servo-Loop method used is aimed at the non-linearity extraction of static ADC transfer curve; in this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. Powerful capabilities of the proposed VTE were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre. (en)
Title	Experience in Virtual Testing of RSD Cyclic A/D converters Experience in Virtual Testing of RSD Cyclic A/D converters (en)
skos:prefLabel	Experience in Virtual Testing of RSD Cyclic A/D converters Experience in Virtual Testing of RSD Cyclic A/D converters (en)
skos:notation	RIV/68407700:21230/09:00157681!RIV10-MSM-21230___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/07/1186), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat	2010
http://linked.open...aciTvurceVysledku	Šubrt, Ondřej Martinek, Pravoslav Jakovenko, Jiří Kubař, Miloslav
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	314165
http://linked.open...ai/riv/idVysledku	RIV/68407700:21230/09:00157681
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Servo-loop method; Verilog-A; Cyclic RSD A/D Converter; Virtual ADC testing; INL; DNL (en)
http://linked.open.../riv/klicoveSlovo	INL DNL Cyclic RSD A/D Converter Servo-loop method Verilog-A Virtual ADC testing
http://linked.open...ontrolniKodProRIV	[9AD73050D043]
http://linked.open...v/mistoKonaniAkce	Liberec
http://linked.open...i/riv/mistoVydani	Los Alamitos
http://linked.open...i/riv/nazevZdroje	Proc. of 12th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2009 (DDECS'09)
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	4 (xsd:int)
http://linked.open...cetTvurcuVysledku	4 (xsd:int)
http://linked.open...vavai/riv/projekt	Sophisticated methods of the analog and mixed-signal circuits design in sub-micron technologies
http://linked.open...UplatneniVysledku	2009
http://linked.open...iv/tvurceVysledku	Martinek, Pravoslav Šubrt, Ondřej Jakovenko, Jiří Kubař, Miloslav
http://linked.open...vavai/riv/typAkce	EUR - Evropská
http://linked.open.../riv/zahajeniAkce	2009-04-15 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum perspektivních informačních a komunikačních technologií
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society Press
https://schema.org/isbn	978-1-4244-3339-1
http://localhost/t...ganizacniJednotka	21230

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