About: Dependable design technique for system-on-chip

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters. A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters. (en) A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters. (cs)
Title	Dependable design technique for system-on-chip Metodologie spolehliveho navrhu pro systemy na cipu (cs) Dependable design technique for system-on-chip (en)
skos:prefLabel	Dependable design technique for system-on-chip Metodologie spolehliveho navrhu pro systemy na cipu (cs) Dependable design technique for system-on-chip (en)
skos:notation	RIV/68407700:21230/08:03144365!RIV09-MSM-21230___
http://linked.open...avai/riv/aktivita	Z
http://linked.open...avai/riv/aktivity	Z(MSM6840770014)
http://linked.open...iv/cisloPeriodika	54
http://linked.open...vai/riv/dodaniDat	2009
http://linked.open...aciTvurceVysledku	Kubátová, Hana Kubalík, Pavel
http://linked.open.../riv/druhVysledku	J - Článek v odborném periodiku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	362519
http://linked.open...ai/riv/idVysledku	RIV/68407700:21230/08:03144365
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Fault security; Self-testing; Totally selfchecking; Reliable digital design; FPGA; Dependability model; Dependability calculations; On-line testing (en)
http://linked.open.../riv/klicoveSlovo	FPGA On-line testing Dependability calculations Dependability model Fault security Reliable digital design Self-testing Totally selfchecking
http://linked.open...odStatuVydavatele	NL - Nizozemsko
http://linked.open...ontrolniKodProRIV	[D080CC39C69D]
http://linked.open...i/riv/nazevZdroje	Journal of Systems Architecture
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...UplatneniVysledku	2008
http://linked.open...v/svazekPeriodika	2008
http://linked.open...iv/tvurceVysledku	Kubátová, Hana Kubalík, Pavel
http://linked.open...ain/vavai/riv/wos	000256705500009
http://linked.open...n/vavai/riv/zamer	Výzkum perspektivních informačních a komunikačních technologií
issn	1383-7621
number of pages	13 (xsd:int)
http://localhost/t...ganizacniJednotka	21230

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