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  • We propose a method to efficiently design a %22parity generator%22, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designed by duplicating the original circuit, XOR-ing given groups of its outputs and resynthesizing the whole circuit. The resulting circuitry is mostly smaller than the original circuit. The major task to be solved is to properly select the groups of outputs to be XORed to obtain multiple parity bits and maximally reduce the generator size. A method based on principles of the FC-Min minimizer is proposed in this paper. The parity generator is exploited in on line diagnostics, to design self-checking circuits based on a modified duplex system.
  • We propose a method to efficiently design a %22parity generator%22, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designed by duplicating the original circuit, XOR-ing given groups of its outputs and resynthesizing the whole circuit. The resulting circuitry is mostly smaller than the original circuit. The major task to be solved is to properly select the groups of outputs to be XORed to obtain multiple parity bits and maximally reduce the generator size. A method based on principles of the FC-Min minimizer is proposed in this paper. The parity generator is exploited in on line diagnostics, to design self-checking circuits based on a modified duplex system. (en)
Title
  • An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
  • An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA (en)
skos:prefLabel
  • An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
  • An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA (en)
skos:notation
  • RIV/68407700:21230/08:00145451!RIV10-MSM-21230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(FI-IM4/149), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 355644
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/08:00145451
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • FC-Min; On-line testing; Output grouping; Parity prediction (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [D7607BF31444]
http://linked.open...v/mistoKonaniAkce
  • Parma
http://linked.open...i/riv/mistoVydani
  • Los Alamitos
http://linked.open...i/riv/nazevZdroje
  • Proceedings of 11th Euromicro Conference on Digital System Design
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kubátová, Hana
  • Kubalík, Pavel
  • Fišer, Petr
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE Computer Society
https://schema.org/isbn
  • 978-0-7695-3277-6
http://localhost/t...ganizacniJednotka
  • 21230
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