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Description
  • Cilem prace byla realizace IP bloku pro seriovou aritmetiku - seriove scitacky, nasobicky a FIR filtru klouzavych prumeru. Bloky byly vytvoreny v jazyce VHDL, simulovany a jejich technicke parametry jsou uvedeny ve zprave spolu s kraktym srovnanim s paralelnimi aritmetickymi operatory. (cs)
  • The purpose of this project was to create configurable IP cores for serial arithmetic operations. This includes serial adder, serial multiplier and moving average FIR filter. Cores were designed in the VHDL language, verified and their design parameters are presented in the document along with some comparison agains the paralllel arithmetic operators.
  • The purpose of this project was to create configurable IP cores for serial arithmetic operations. This includes serial adder, serial multiplier and moving average FIR filter. Cores were designed in the VHDL language, verified and their design parameters are presented in the document along with some comparison agains the paralllel arithmetic operators. (en)
Title
  • Serial Arithmetic IP cores
  • Serial Arithmetic IP cores (en)
  • IP bloky pro realizaci seriovych aritmetickych operaci (cs)
skos:prefLabel
  • Serial Arithmetic IP cores
  • Serial Arithmetic IP cores (en)
  • IP bloky pro realizaci seriovych aritmetickych operaci (cs)
skos:notation
  • RIV/68407700:21230/07:03131750!RIV09-MSM-21230___
http://linked.open...avai/riv/aktivita
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  • Z(MSM6840770012)
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  • 449520
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  • RIV/68407700:21230/07:03131750
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  • arithmetic IP cores (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [D880F79F3AD9]
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  • Šťastný, Jakub
  • Drinovsky, M.
http://linked.open...n/vavai/riv/zamer
http://localhost/t...ganizacniJednotka
  • 21230
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