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  • Předložený článek navrhuje inovovaný koncept virtuálního testovacího rozhraní pro analogově-číslicové převodníky s využitím vhodného spojení dvou extrakčních algoritmů - Servosmyčkové a histogramové metody. Navržené testovací rozhraní je implementováno v MAPLE a sestává z programových procedur pro extrakci nelinearit ADC. Inovací našeho řešení je využití efektivního vyhledávacího algoritmu a zlepšené konvergenční vlastnosti, přispívající ke značnému zkrácení simulačního času. (cs)
  • This paper proposes an innovative concept of a virtual testing environment for analog-to-digital converters (ADCs) applying a suitable conjunction of two performance extraction algorithms - the Servo-Loop and Histogram method. The testing engine proposed is implemented in MAPLE and consists of program procedures to extract ADC errors expressed in term of integral and differential non-linearity (INL and DNL). The novelty of our solution is the use of effective search algorithm and improved convergence properties resulting in a significant reduction of the simulation time.
  • This paper proposes an innovative concept of a virtual testing environment for analog-to-digital converters (ADCs) applying a suitable conjunction of two performance extraction algorithms - the Servo-Loop and Histogram method. The testing engine proposed is implemented in MAPLE and consists of program procedures to extract ADC errors expressed in term of integral and differential non-linearity (INL and DNL). The novelty of our solution is the use of effective search algorithm and improved convergence properties resulting in a significant reduction of the simulation time. (en)
Title
  • Developing Virtual ADC Testing Environment in MAPLE
  • Developing Virtual ADC Testing Environment in MAPLE (en)
  • Vývoj virtuálního testovacího rozhraní v MAPLE (cs)
skos:prefLabel
  • Developing Virtual ADC Testing Environment in MAPLE
  • Developing Virtual ADC Testing Environment in MAPLE (en)
  • Vývoj virtuálního testovacího rozhraní v MAPLE (cs)
skos:notation
  • RIV/68407700:21230/07:03131192!RIV08-GA0-21230___
http://linked.open.../vavai/riv/strany
  • 417;421
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/07/1186)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 416793
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/07:03131192
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • A/D Converter testing; Behavioral modeling; Design evaluation; Integral and Differential Non-linearity; Servo-Loop and Histogram method (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [73C568753B0C]
http://linked.open...v/mistoKonaniAkce
  • Krakow
http://linked.open...i/riv/mistoVydani
  • Los Alamitos
http://linked.open...i/riv/nazevZdroje
  • Design and Diagnostics of Electronic Circuits and Systems
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Hospodka, Jiří
  • Martinek, Pravoslav
  • Šubrt, Ondřej
  • Struhovský, Petr
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE Computer Society
https://schema.org/isbn
  • 1-4244-1161-0
http://localhost/t...ganizacniJednotka
  • 21230
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