About: Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System     Goto   Sponge   NotDistinct   Permalink

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Description
  • Popis metody injekce a simulace poruch pro rekonfigurovatelný duplexní systém odolný proti poruchám. (cs)
  • The implementation and the fault emulation technique for the highly reliable digital design using Modified Duplex System (MDS) architecture under a processor control is presented. A Totally Self-Checking analysis of MDS architecture is supported by experimental results from our proposed FPGA fault emulator, where SEU-fault resistance is observed. Our proposed hardware fault emulator results are compared also with the software simulation results. An area overhead of individual parts implemented in each FPGA is also discussed.
  • The implementation and the fault emulation technique for the highly reliable digital design using Modified Duplex System (MDS) architecture under a processor control is presented. A Totally Self-Checking analysis of MDS architecture is supported by experimental results from our proposed FPGA fault emulator, where SEU-fault resistance is observed. Our proposed hardware fault emulator results are compared also with the software simulation results. An area overhead of individual parts implemented in each FPGA is also discussed. (en)
Title
  • Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System
  • Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System (en)
  • Injekce a simulace poruch pro rekonfigurovatelný duplexní systém odolný proti poruchám (cs)
skos:prefLabel
  • Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System
  • Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System (en)
  • Injekce a simulace poruch pro rekonfigurovatelný duplexní systém odolný proti poruchám (cs)
skos:notation
  • RIV/68407700:21230/07:03130529!RIV08-MSM-21230___
http://linked.open.../vavai/riv/strany
  • 357;360
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 421744
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/07:03130529
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • hardware fault emulation, fault tolerant design, digital design (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [FABBBD7CF31A]
http://linked.open...v/mistoKonaniAkce
  • Krakow
http://linked.open...i/riv/mistoVydani
  • Los Alamitos
http://linked.open...i/riv/nazevZdroje
  • Design and Diagnostics of Electronic Circuits and Systems
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kvasnička, Jiří
  • Kubátová, Hana
  • Kubalík, Pavel
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE Computer Society
https://schema.org/isbn
  • 1-4244-1161-0
http://localhost/t...ganizacniJednotka
  • 21230
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