About: Scheduling of Tasks with Precedence Delays and Relative Deadlines - Framework for Time-optimal Dynamic Reconfiguration of FPGAs     Goto   Sponge   NotDistinct   Permalink

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  • Není k dispozici (cs)
  • This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To facilitate the design process we present an optimal scheduling algorithm using a very universal framework, where tasks are constrained by precedence delays and relative deadlines. The NP-hard problem of finding an optimal schedule satisfying the timing and resource constraints while minimizing the makespan Cmax, is solved using two approaches. The first one is based on Integer Linear Programming and the second one is implemented as a Branch and Bound algorithm. Experimental results show the efficiency comparison of the ILP and Branch and Bound solutions.
  • This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To facilitate the design process we present an optimal scheduling algorithm using a very universal framework, where tasks are constrained by precedence delays and relative deadlines. The NP-hard problem of finding an optimal schedule satisfying the timing and resource constraints while minimizing the makespan Cmax, is solved using two approaches. The first one is based on Integer Linear Programming and the second one is implemented as a Branch and Bound algorithm. Experimental results show the efficiency comparison of the ILP and Branch and Bound solutions. (en)
Title
  • Scheduling of Tasks with Precedence Delays and Relative Deadlines - Framework for Time-optimal Dynamic Reconfiguration of FPGAs
  • Není k dispozici (cs)
  • Scheduling of Tasks with Precedence Delays and Relative Deadlines - Framework for Time-optimal Dynamic Reconfiguration of FPGAs (en)
skos:prefLabel
  • Scheduling of Tasks with Precedence Delays and Relative Deadlines - Framework for Time-optimal Dynamic Reconfiguration of FPGAs
  • Není k dispozici (cs)
  • Scheduling of Tasks with Precedence Delays and Relative Deadlines - Framework for Time-optimal Dynamic Reconfiguration of FPGAs (en)
skos:notation
  • RIV/68407700:21230/06:03128484!RIV07-MSM-21230___
http://linked.open.../vavai/riv/strany
  • 170 ; 170
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  • P(1M0567)
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  • 498524
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  • RIV/68407700:21230/06:03128484
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  • FPGA; Rapid prototyping; reconfiguration; sheduling (en)
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  • [5A257913377A]
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  • Rhodos
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  • New York
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  • IEEE International Parallel & Distributed Processing Symposium
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  • Hanzálek, Zdeněk
  • Šůcha, Přemysl
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number of pages
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  • IEEE Press
https://schema.org/isbn
  • 1-4244-0054-6
http://localhost/t...ganizacniJednotka
  • 21230
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