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  • Není k dispozici (cs)
  • This paper deals with design methodology of high reliable digital system based on modified duplex system. Our modified duplex system is based on two FPGAs, where every FPGA can be reconfigured when a fault is detected. Design implemented in each FPGAs is based on one of several methods how to ensure the self checking properties. Our design methodology reflects requirements on area overhead and value of dependability parameters. Our modified duplex system is compared with standard duplex system. Our dependability model and dependability calculations are used to quantify proposed solutions. Availability parameters have been calculated by dependability Markov models. The final reliable system is fault tolerant.
  • This paper deals with design methodology of high reliable digital system based on modified duplex system. Our modified duplex system is based on two FPGAs, where every FPGA can be reconfigured when a fault is detected. Design implemented in each FPGAs is based on one of several methods how to ensure the self checking properties. Our design methodology reflects requirements on area overhead and value of dependability parameters. Our modified duplex system is compared with standard duplex system. Our dependability model and dependability calculations are used to quantify proposed solutions. Availability parameters have been calculated by dependability Markov models. The final reliable system is fault tolerant. (en)
Title
  • Design Methodology for High Reliable System
  • Není k dispozici (cs)
  • Design Methodology for High Reliable System (en)
skos:prefLabel
  • Design Methodology for High Reliable System
  • Není k dispozici (cs)
  • Design Methodology for High Reliable System (en)
skos:notation
  • RIV/68407700:21230/06:03121486!RIV07-GA0-21230___
http://linked.open.../vavai/riv/strany
  • 274 ; 279
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/04/0737), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
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http://linked.open...dnocenehoVysledku
  • 470920
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/06:03121486
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • TSC circuit, reliability, dependability, fault-tolerant, FPGA (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [4AFE13736A2B]
http://linked.open...v/mistoKonaniAkce
  • Herl'any
http://linked.open...i/riv/mistoVydani
  • Ko1ice
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the Seventh International Scientific Conference on Electronic Computers and Informatics ECI 2006
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kubátová, Hana
  • Kubalík, Pavel
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • Technická univerzita v Košiciach
https://schema.org/isbn
  • 80-8073-598-0
http://localhost/t...ganizacniJednotka
  • 21230
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