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Description
  • Není k dispozici (cs)
  • A technique for highly reliable digital design in FPGAs is presented. Two FPGAs are used for duplex system design, but better dependability parameters are obtained by combination of totally self checking blocks based on parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained by XILINX FPGA implementation by EDA tools. The dependability model and dependability calculations are presented.
  • A technique for highly reliable digital design in FPGAs is presented. Two FPGAs are used for duplex system design, but better dependability parameters are obtained by combination of totally self checking blocks based on parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained by XILINX FPGA implementation by EDA tools. The dependability model and dependability calculations are presented. (en)
Title
  • Dependable Design for FPGA based on Duplex System and Reconfiguration
  • Není k dispozici (cs)
  • Dependable Design for FPGA based on Duplex System and Reconfiguration (en)
skos:prefLabel
  • Dependable Design for FPGA based on Duplex System and Reconfiguration
  • Není k dispozici (cs)
  • Dependable Design for FPGA based on Duplex System and Reconfiguration (en)
skos:notation
  • RIV/68407700:21230/06:03121358!RIV07-GA0-21230___
http://linked.open.../vavai/riv/strany
  • 139 ; 145
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/04/2137), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 470785
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/06:03121358
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • dependability, reconfiguration, FPGA, on-line testing (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [2AF755291403]
http://linked.open...v/mistoKonaniAkce
  • Cavtat
http://linked.open...i/riv/mistoVydani
  • Los Alamitos
http://linked.open...i/riv/nazevZdroje
  • Proceedings of 9th Euromicro Conference on Digital System Design
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kubátová, Hana
  • Kubalík, Pavel
  • Dobiá1, Radek
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE Computer Society
https://schema.org/isbn
  • 0-7695-2609-8
http://localhost/t...ganizacniJednotka
  • 21230
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