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Description
  • This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults.
  • This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults. (en)
  • This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults. (cs)
Title
  • Fault Tolerant System Design Method Based on Self-Checking Circuits
  • Fault Tolerant System Design Method Based on Self-Checking Circuits (en)
  • Fault Tolerant System Design Method Based on Self-Checking Circuits (cs)
skos:prefLabel
  • Fault Tolerant System Design Method Based on Self-Checking Circuits
  • Fault Tolerant System Design Method Based on Self-Checking Circuits (en)
  • Fault Tolerant System Design Method Based on Self-Checking Circuits (cs)
skos:notation
  • RIV/68407700:21230/06:03120136!RIV07-GA0-21230___
http://linked.open.../vavai/riv/strany
  • 185 ; 186
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/04/0737), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 475636
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/06:03120136
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • FPGA, reconfiguration, fault tolerance, self-checking circuit (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [196F9C688A93]
http://linked.open...v/mistoKonaniAkce
  • Como
http://linked.open...i/riv/mistoVydani
  • Los Alamitos
http://linked.open...i/riv/nazevZdroje
  • Proceedings IOLTS 2006 12th IEEE International On-Line Testing Symposium
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kubátová, Hana
  • Kubalík, Pavel
  • Fi1er, Petr
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE Computer Society
https://schema.org/isbn
  • 0-7695-2620-9
http://localhost/t...ganizacniJednotka
  • 21230
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