About: Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process     Goto   Sponge   NotDistinct   Permalink

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Description
  • Our backward-determining structure generates all valid input vectors to an applied output vector, an input vector is generated during only one clock cycle, two variants of reconfiguration for speeding up the vector generation, experimental data obtained for ISCAS'85. Reconfiguration usage for small circuits is not effective enough (average area overhead is about 120 %, average speed up is about 9.3 %), but for large circuits is acceptable (average area overhead is about 96 %, average speed up is about 21.5 %).
  • Our backward-determining structure generates all valid input vectors to an applied output vector, an input vector is generated during only one clock cycle, two variants of reconfiguration for speeding up the vector generation, experimental data obtained for ISCAS'85. Reconfiguration usage for small circuits is not effective enough (average area overhead is about 120 %, average speed up is about 9.3 %), but for large circuits is acceptable (average area overhead is about 96 %, average speed up is about 21.5 %). (en)
  • Námi navr3ená zpitni-odvozující struktura generuje v1echny platné vstupní vektory k poilo3enému výstupnímu vektoru, vstupní vektor je generován bihem pouze jednoho hodinového cyklu, dvi varianty rekonfigurace pro zrychlení generování vektoru, experimentální data získána nad ISCAS'85. Vyu3ití rekonfigurace pro malé obvody není dostateeni efektivní (prumirná prostorová slo3itost je okolo 120 %, prumirné zrychlení je v1ak pouze okolo 9,3 %), ale pro velké obvody je poijatelný (prumirná prostorová slo3itost je okolo 96 %, prumirné zrychlení je okolo 21,5 %). (cs)
Title
  • Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process
  • Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process (en)
  • Rekonfigurace backtrace algoritmu implementovaného v HW pro zrychlení procesu generování vektoru (cs)
skos:prefLabel
  • Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process
  • Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process (en)
  • Rekonfigurace backtrace algoritmu implementovaného v HW pro zrychlení procesu generování vektoru (cs)
skos:notation
  • RIV/68407700:21230/06:03119432!RIV07-GA0-21230___
http://linked.open.../vavai/riv/strany
  • 59 ; 64
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/04/2137), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 496734
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/06:03119432
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • backtrace; hardware; reconfiguration; scan design; vector generation (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [FF7567632EF7]
http://linked.open...v/mistoKonaniAkce
  • Cluj-Napoca
http://linked.open...i/riv/mistoVydani
  • Piscataway
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the 2006 IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Novák, Ondřej
  • Šťáva, Martin
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE
https://schema.org/isbn
  • 1-4244-0360-X
http://localhost/t...ganizacniJednotka
  • 21230
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