About: Parity Codes Used for On-line Testing in FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes. The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented. This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes. The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented. (en) This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes. The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented. (cs)
Title	Parity Codes Used for On-line Testing in FPGA Parity Codes Used for On-line Testing in FPGA (en) Parity Codes Used for On-line Testing in FPGA (cs)
skos:prefLabel	Parity Codes Used for On-line Testing in FPGA Parity Codes Used for On-line Testing in FPGA (en) Parity Codes Used for On-line Testing in FPGA (cs)
skos:notation	RIV/68407700:21230/05:03117292!RIV06-MSM-21230___
http://linked.open.../vavai/riv/strany	53 ; 59
http://linked.open...avai/riv/aktivita	Z
http://linked.open...avai/riv/aktivity	Z(MSM6840770014)
http://linked.open...iv/cisloPeriodika	6
http://linked.open...vai/riv/dodaniDat	2006
http://linked.open...aciTvurceVysledku	Kubátová, Hana Kubalík, Pavel
http://linked.open.../riv/druhVysledku	J - Článek v odborném periodiku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	535439
http://linked.open...ai/riv/idVysledku	RIV/68407700:21230/05:03117292
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	On-line testing, self-checking, error detection code, fault, error, FPGA (en)
http://linked.open.../riv/klicoveSlovo	FPGA error self-checking On-line testing fault error detection code
http://linked.open...odStatuVydavatele	CZ - Česká republika
http://linked.open...ontrolniKodProRIV	[6DF0B0D7A410]
http://linked.open...i/riv/nazevZdroje	Acta Polytechnica
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...UplatneniVysledku	2005
http://linked.open...v/svazekPeriodika	45
http://linked.open...iv/tvurceVysledku	Kubátová, Hana Kubalík, Pavel
http://linked.open...n/vavai/riv/zamer	Výzkum perspektivních informačních a komunikačních technologií
issn	1210-2709
number of pages	7 (xsd:int)
http://localhost/t...ganizacniJednotka	21230

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