About: Design Retiming in HDL

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Není k dispozici (cs) This paper deals with an improvement of design timing characteristics by modification at the high abstraction level of the system description. Some synthesis tools such as Synplify Pro provide timing optimizations, called pipelining and retiming. These techniques help the designer unify delay slacks at different inputs, which results in higher system clock frequencies of the produced circuit. Unfortunately these techniques are not available for all devices, for example Atmel FPGAs are not supported. A modification at HDL level is the way how to achieve slight improvement for these devices. This paper deals with an improvement of design timing characteristics by modification at the high abstraction level of the system description. Some synthesis tools such as Synplify Pro provide timing optimizations, called pipelining and retiming. These techniques help the designer unify delay slacks at different inputs, which results in higher system clock frequencies of the produced circuit. Unfortunately these techniques are not available for all devices, for example Atmel FPGAs are not supported. A modification at HDL level is the way how to achieve slight improvement for these devices. (en)
Title	Design Retiming in HDL Design Retiming in HDL (en) Design Retiming in HDL (cs)
skos:prefLabel	Design Retiming in HDL Design Retiming in HDL (en) Design Retiming in HDL (cs)
skos:notation	RIV/68407700:21230/05:03110088!RIV06-GA0-21230___
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(GA102/04/2137)
http://linked.open...vai/riv/dodaniDat	2006
http://linked.open...aciTvurceVysledku	Matoušek, Rudolf Kafka, Leoš
http://linked.open.../riv/druhVysledku	A(V) - Audiovizuální tvorba se vzdáleným přístupem
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	517423
http://linked.open...ai/riv/idVysledku	RIV/68407700:21230/05:03110088
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	FPGA; HDL (en)
http://linked.open.../riv/klicoveSlovo	FPGA HDL
http://linked.open...i/riv/kodPristupu	L
http://linked.open...ontrolniKodProRIV	[B3220181C1A3]
http://linked.open...i/riv/mistoVydani	Praha
http://linked.open...n/vavai/riv/nosic	neuvedeno
http://linked.open...in/vavai/riv/obor	IN
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Design of highly reliable control systems built on dynamically reconfigurable FPGAs.
http://linked.open...UplatneniVysledku	2005
http://linked.open...iv/tvurceVysledku	Kafka, Leoš Matoušek, Rudolf
https://schema.org/isbn	80-01-03201-9
http://localhost/t...ganizacniJednotka	21230

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