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  • Článek se zabýva návrhem vysoce spolehlivých obvod implementovaných pomocí FPGA obvodů. Návrh je založen na jednoduchém zdvojení obvodů splňujících podminky pro návrh TSC obvodu. (cs)
  • This paper deals with architecture of highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. A duplex system is used as a basic structure of this reliable design. The whole design implemented in FPGA is divided into individual functional parts. Every part is modified to ensure totally self checking properties, which are calculated using our method of detailed fault classification. The reconfiguration process is utilized to increase reliability parameters. Combinational circuit benchmarks have been considered in this work to compute the quality of the adapted duplex system. The benchmarks are represented by two level networks (truth table). All of our experimental results are obtained by XILINX FPGA implementation by EDA tools.
  • This paper deals with architecture of highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. A duplex system is used as a basic structure of this reliable design. The whole design implemented in FPGA is divided into individual functional parts. Every part is modified to ensure totally self checking properties, which are calculated using our method of detailed fault classification. The reconfiguration process is utilized to increase reliability parameters. Combinational circuit benchmarks have been considered in this work to compute the quality of the adapted duplex system. The benchmarks are represented by two level networks (truth table). All of our experimental results are obtained by XILINX FPGA implementation by EDA tools. (en)
Title
  • Highly Reliable Design Based on TSC Circuits
  • Highly Reliable Design Based on TSC Circuits (en)
  • Vysoce spolehlivý návrh TSC obvodů (cs)
skos:prefLabel
  • Highly Reliable Design Based on TSC Circuits
  • Highly Reliable Design Based on TSC Circuits (en)
  • Vysoce spolehlivý návrh TSC obvodů (cs)
skos:notation
  • RIV/68407700:21230/05:03109967!RIV06-GA0-21230___
http://linked.open.../vavai/riv/strany
  • 101 ; 106
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/03/0672), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 523314
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/05:03109967
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • FPGA, tottaly self-checking (TSC) circuit, dependability, concurrent error detection (CED) (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [10459FE9436E]
http://linked.open...v/mistoKonaniAkce
  • Lázně Sedmihorky
http://linked.open...i/riv/mistoVydani
  • Praha
http://linked.open...i/riv/nazevZdroje
  • Počítačové architektury & diagnostika
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kubátová, Hana
  • Kubalík, Pavel
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • České vysoké učení technické v Praze. Fakulta elektrotechnická. Katedra počítačů
https://schema.org/isbn
  • 80-01-03298-1
http://localhost/t...ganizacniJednotka
  • 21230
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