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Description
  • Není k dispozici (cs)
  • Our paper describes a new structure of design for FPGAs which improves reliability parameters and preserves lower area overhead than the classical methods such as duplication or triplication. Our solution assumes the possibility of dynamic reconfiguration of the faulty part. The most important criterion is the speed of the fault detection and the safety of the whole circuit with respect to the surrounding environment. Our methodology enables cooperation between on-line methods and off-line BIST methods for fault detection and localization.
  • Our paper describes a new structure of design for FPGAs which improves reliability parameters and preserves lower area overhead than the classical methods such as duplication or triplication. Our solution assumes the possibility of dynamic reconfiguration of the faulty part. The most important criterion is the speed of the fault detection and the safety of the whole circuit with respect to the surrounding environment. Our methodology enables cooperation between on-line methods and off-line BIST methods for fault detection and localization. (en)
Title
  • Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs
  • Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs (en)
  • Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs (cs)
skos:prefLabel
  • Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs
  • Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs (en)
  • Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs (cs)
skos:notation
  • RIV/68407700:21230/05:03109883!RIV06-GA0-21230___
http://linked.open.../vavai/riv/strany
  • 13 ; 14
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/03/0672), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 540329
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/05:03109883
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • fault tolerance, duplex, reconfiguration, FPGA (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [592C3389AD70]
http://linked.open...v/mistoKonaniAkce
  • Porto
http://linked.open...i/riv/mistoVydani
  • Linz
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the Work in Progress Session
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kubátová, Hana
  • Kubalík, Pavel
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • Johannes Kepler University
https://schema.org/isbn
  • 3-902457-09-0
http://localhost/t...ganizacniJednotka
  • 21230
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