About: Fault Classification for Self-checking Circuits Implemented in FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Není k dispozici (cs) This paper focuses on a fault classification problem for concurrent error detection circuits based on error detecting codes. The proposed fault classification differs from the common classification, where the faults are divided into two groups - the testable faults and the untestable faults. The faults are divided into four groups in our approach, by their impact to fault secure and self-testing properties. Our fault simulation software has been used to evaluate the proposed fault classification on real benchmarks. The benchmarks were implemented in a FPGA, and stuck-at-1 and stuck-at-0 fault model has been considered. This paper focuses on a fault classification problem for concurrent error detection circuits based on error detecting codes. The proposed fault classification differs from the common classification, where the faults are divided into two groups - the testable faults and the untestable faults. The faults are divided into four groups in our approach, by their impact to fault secure and self-testing properties. Our fault simulation software has been used to evaluate the proposed fault classification on real benchmarks. The benchmarks were implemented in a FPGA, and stuck-at-1 and stuck-at-0 fault model has been considered. (en)
Title	Fault Classification for Self-checking Circuits Implemented in FPGA Není k dispozici (cs) Fault Classification for Self-checking Circuits Implemented in FPGA (en)
skos:prefLabel	Fault Classification for Self-checking Circuits Implemented in FPGA Není k dispozici (cs) Fault Classification for Self-checking Circuits Implemented in FPGA (en)
skos:notation	RIV/68407700:21230/05:03108032!RIV06-GA0-21230___
http://linked.open.../vavai/riv/strany	228 ; 231
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/04/2137), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat	2006
http://linked.open...aciTvurceVysledku	Kafka, Leoš Novák, Ondřej Kubátová, Hana Kubalík, Pavel
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	521445
http://linked.open...ai/riv/idVysledku	RIV/68407700:21230/05:03108032
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	fault security, self-testing, fault tolerant,, digital design. testing, FPGA (en)
http://linked.open.../riv/klicoveSlovo	FPGA fault tolerant digital design. testing fault security self-testing
http://linked.open...ontrolniKodProRIV	[D7866F3DC291]
http://linked.open...v/mistoKonaniAkce	Sopron
http://linked.open...i/riv/mistoVydani	Sopron
http://linked.open...i/riv/nazevZdroje	Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	4 (xsd:int)
http://linked.open...cetTvurcuVysledku	4 (xsd:int)
http://linked.open...vavai/riv/projekt	Design of highly reliable control systems built on dynamically reconfigurable FPGAs.
http://linked.open...UplatneniVysledku	2005
http://linked.open...iv/tvurceVysledku	Kafka, Leoš Novák, Ondřej Kubátová, Hana Kubalík, Pavel
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2005-04-13 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum perspektivních informačních a komunikačních technologií
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	University of Western Hungary
https://schema.org/isbn	963-9364-48-7
http://localhost/t...ganizacniJednotka	21230

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