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  • This article deals with a distributed, fault-tolerant real-time application modeling by timed automata. The application under consideration consists of several processors communicating via Controller Area Network (CAN); each processor executes an application that consists of fault-tolerant tasks running under an operating system (e.g. OSEK) and using inter-task synchronization primitives. For such system, the model checking tool (e.g. UPAALL) can be used to verify complex time and logical properties formalized as a safety or bounded liveness properties (e.g. end-to-end response time considering occurrence of a fault, state reachability).The main contribution of this paper is that the proposed model reduces size of the state-space by sharing clocks measuring the execution time of tasks and simply incorporates fault-tolerant features of the application.
  • This article deals with a distributed, fault-tolerant real-time application modeling by timed automata. The application under consideration consists of several processors communicating via Controller Area Network (CAN); each processor executes an application that consists of fault-tolerant tasks running under an operating system (e.g. OSEK) and using inter-task synchronization primitives. For such system, the model checking tool (e.g. UPAALL) can be used to verify complex time and logical properties formalized as a safety or bounded liveness properties (e.g. end-to-end response time considering occurrence of a fault, state reachability).The main contribution of this paper is that the proposed model reduces size of the state-space by sharing clocks measuring the execution time of tasks and simply incorporates fault-tolerant features of the application. (en)
Title
  • Timed Automata Approach to Distributed and Fault Tolerant System Verification
  • Timed Automata Approach to Distributed and Fault Tolerant System Verification (en)
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  • Timed Automata Approach to Distributed and Fault Tolerant System Verification
  • Timed Automata Approach to Distributed and Fault Tolerant System Verification (en)
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  • RIV/68407700:21230/05:00110220!RIV14-MSM-21230___
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  • 546824
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  • RIV/68407700:21230/05:00110220
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  • Controller area network; Distributed system; Model checking; Real-Time system; Timed automata (en)
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  • [E2F56D3D2C47]
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  • Hanzálek, Zdeněk
  • Waszniowski, Libor
  • Krákora, Jan
http://localhost/t...ganizacniJednotka
  • 21230
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