About: Fault Tolerant Design Methodology

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Není k dispozici (cs) This paper focuses on the on-line error detection in circuits implemented in FPGAs. We have used error detection codes to ensure the self-checking property. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Only combinational circuits are considered. The benchmarks used in this work in order to compute a quality of the used code, are described by equations instead of tables, mainly used. All of our experiments assume their XILINX FPGA implementation. Due to their further implementation in FPGAs the fault model considers that the configuration data are stored in the configuration memory. This work is a part of a more complex methodology of a fault tolerant design based on FPGAs with dynamical reconfiguration of the faulty part of the designed circuit. This paper focuses on the on-line error detection in circuits implemented in FPGAs. We have used error detection codes to ensure the self-checking property. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Only combinational circuits are considered. The benchmarks used in this work in order to compute a quality of the used code, are described by equations instead of tables, mainly used. All of our experiments assume their XILINX FPGA implementation. Due to their further implementation in FPGAs the fault model considers that the configuration data are stored in the configuration memory. This work is a part of a more complex methodology of a fault tolerant design based on FPGAs with dynamical reconfiguration of the faulty part of the designed circuit. (en)
Title	Není k dispozici (cs) Fault Tolerant Design Methodology Fault Tolerant Design Methodology (en)
skos:prefLabel	Není k dispozici (cs) Fault Tolerant Design Methodology Fault Tolerant Design Methodology (en)
skos:notation	RIV/68407700:21230/04:03107162!RIV/2005/GA0/212305/N
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/04/2137), Z(MSM 212300014)
http://linked.open...vai/riv/dodaniDat	2005
http://linked.open...aciTvurceVysledku	Kubalík, Pavel
http://linked.open.../riv/druhVysledku	A(V) - Audiovizuální tvorba se vzdáleným přístupem
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	564217
http://linked.open...ai/riv/idVysledku	RIV/68407700:21230/04:03107162
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	FPGA, on-line testing, fault-tolerance, error detection codes (en)
http://linked.open.../riv/klicoveSlovo	fault-tolerance on-line testing FPGA error detection codes
http://linked.open...i/riv/kodPristupu	L
http://linked.open...ontrolniKodProRIV	[B578399FEBD9]
http://linked.open...i/riv/mistoVydani	Praha
http://linked.open...n/vavai/riv/nosic	neuvedeno
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	1 (xsd:int)
http://linked.open...vavai/riv/projekt	Design of highly reliable control systems built on dynamically reconfigurable FPGAs.
http://linked.open...UplatneniVysledku	2004
http://linked.open...iv/tvurceVysledku	Kubalík, Pavel
http://linked.open...n/vavai/riv/zamer	http://linked.opendata.cz/resource/domain/vavai/zamer/MSM%20212300014
http://localhost/t...ganizacniJednotka	21230

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