About: Reducing Instruction Issue Overheads in Application-Specific Vector Processors

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. Previously we proposed a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. In our setting we employ an embedded simple scalar CPU (8-bit PicoBlaze 3) to control a floating-point vector processing unit (VPU) by issuing wide (horizontally encoded) instructions to it. In this work we dramatically reduce the overhead of the wide-instruction issue (in one case by 13x) by implementing a new two-level configuration table. The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. Previously we proposed a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. In our setting we employ an embedded simple scalar CPU (8-bit PicoBlaze 3) to control a floating-point vector processing unit (VPU) by issuing wide (horizontally encoded) instructions to it. In this work we dramatically reduce the overhead of the wide-instruction issue (in one case by 13x) by implementing a new two-level configuration table. (en)
Title	Reducing Instruction Issue Overheads in Application-Specific Vector Processors Reducing Instruction Issue Overheads in Application-Specific Vector Processors (en)
skos:prefLabel	Reducing Instruction Issue Overheads in Application-Specific Vector Processors Reducing Instruction Issue Overheads in Application-Specific Vector Processors (en)
skos:notation	RIV/67985556:_____/12:00380442!RIV13-MSM-67985556
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(7H10001)
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Kohout, Lukáš Sýkora, Jaroslav Daněk, Martin Bartosinski, Roman
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Ústav teorie informace a automatizace AV ČR, v. v. i.
http://linked.open...dnocenehoVysledku	164483
http://linked.open...ai/riv/idVysledku	RIV/67985556:_____/12:00380442
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	custom accelerators; vector processing; FPGA; DSP (en)
http://linked.open.../riv/klicoveSlovo	FPGA custom accelerators DSP vector processing
http://linked.open...ontrolniKodProRIV	[ED5F06249C81]
http://linked.open...v/mistoKonaniAkce	Cesme
http://linked.open...i/riv/mistoVydani	Izmir
http://linked.open...i/riv/nazevZdroje	Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	4 (xsd:int)
http://linked.open...cetTvurcuVysledku	5 (xsd:int)
http://linked.open...vavai/riv/projekt	Smart Multicore Embedded SYstems
http://linked.open...UplatneniVysledku	2012
http://linked.open...iv/tvurceVysledku	Daněk, Martin Kohout, Lukáš Sýkora, Jaroslav Honzík, P. Bartosinski, Roman
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2012-09-05 (xsd:date)
number of pages	8 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Conference Publishing Services
https://schema.org/isbn	978-0-7695-4798-5

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