About: Reconfigurable Hardware Objects for Image Processing on FPGAs

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Embedded systems are getting more complex; that is why the high level of abstraction is required during the development process. High abstraction methods simplify implementation of complex computation systems and shorten the time to market. This paper presents an implementation of a graphic computing element (GCE) which can be used as a runtime parametrized building block in image processing applications in FPGAs. In terms of the object oriented model GCE encapsulates its internal data representation and rules for their manipulation. Several basic image processing operations have been implemented (Sobel edge detection, Gauss, mean, etc. filtering). These operations are called as GCE methods. Because of high spatial dependency of image data in image processing, an efficient image data reuse method has been implemented. Embedded systems are getting more complex; that is why the high level of abstraction is required during the development process. High abstraction methods simplify implementation of complex computation systems and shorten the time to market. This paper presents an implementation of a graphic computing element (GCE) which can be used as a runtime parametrized building block in image processing applications in FPGAs. In terms of the object oriented model GCE encapsulates its internal data representation and rules for their manipulation. Several basic image processing operations have been implemented (Sobel edge detection, Gauss, mean, etc. filtering). These operations are called as GCE methods. Because of high spatial dependency of image data in image processing, an efficient image data reuse method has been implemented. (en)
Title	Reconfigurable Hardware Objects for Image Processing on FPGAs Reconfigurable Hardware Objects for Image Processing on FPGAs (en)
skos:prefLabel	Reconfigurable Hardware Objects for Image Processing on FPGAs Reconfigurable Hardware Objects for Image Processing on FPGAs (en)
skos:notation	RIV/67985556:_____/10:00342301!RIV11-MSM-67985556
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(7H09005), Z(AV0Z10750506)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Honzík, Petr Kloub, Jan Daněk, Martin
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Ústav teorie informace a automatizace AV ČR, v. v. i.
http://linked.open...dnocenehoVysledku	284208
http://linked.open...ai/riv/idVysledku	RIV/67985556:_____/10:00342301
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Image Processing; Reconfiguration; Hardware Object; FPGA (en)
http://linked.open.../riv/klicoveSlovo	Reconfiguration FPGA Image Processing Hardware Object
http://linked.open...ontrolniKodProRIV	[F765F2AB50EB]
http://linked.open...v/mistoKonaniAkce	Vienna
http://linked.open...i/riv/mistoVydani	Vienna
http://linked.open...i/riv/nazevZdroje	Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	SCAlable LOw Power Embedded platformS
http://linked.open...UplatneniVysledku	2010
http://linked.open...iv/tvurceVysledku	Daněk, Martin Kloub, Jan Honzík, Petr
http://linked.open...vavai/riv/typAkce	EUR - Evropská
http://linked.open.../riv/zahajeniAkce	2010-04-14 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Pokročilé matematické metody získávání, zpracování a využití informací a znalostí ve složitých a nedeterministických systémech
number of pages	2 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Institute of Electrical and Electronics Engineers
https://schema.org/isbn	978-1-4244-6610-8

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